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PCA8550DRE4 Datasheet

  • PCA8550DRE4

  • NONVOLATILE 5-BIT REGISTER WITH I2C INTERFACE

  • 209.07KB

  • 12頁

  • TI

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PCA8550
NONVOLATILE 5-BIT REGISTER
WITH I
2
C INTERFACE
www.ti.com
SCPS050C 鈥?MARCH 1999 鈥?REVISED MAY 2005
FEATURES
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鈥?/div>
EPIC鈩?(Enhanced-Performance Implanted
CMOS) Submicron Process
Useful for Jumperless Configuration of PC
Motherboard
Inputs Accept Voltages to 5.5 V
MUX OUT Signals are 2.5-V Outputs
NON-MUXED OUT Signal is a 3.3-V Output
Minimum of 1000 Write Cycles
Minimum of 10 Years Data Retention
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline (DB),
and Thin Shrink Small-Outline (PW) Packages
D, DB, OR PW PACKAGE
(TOP VIEW)
I
2
C SCL
I
2
C SDA
OVERRIDE
MUX IN A
MUX IN B
MUX IN C
MUX IN D
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
WP
NON-MUXED OUT
MUX SELECT
MUX OUT A
MUX OUT B
MUX OUT C
MUX OUT D
DESCRIPTION/ORDERING INFORMATION
This 4-bit 1-of-2 multiplexer with I
2
C input interface is designed for 3-V to 3.6-V V
CC
operation.
The PCA8550 is designed to multiplex four bits of data from parallel inputs or from I
2
C input data stored in a
nonvolatile register. An additional bit of register output also is provided, which is latched to prevent changes in
the output value during the write cycle. The factory default for the contents of the register is all low. These stored
values can be read from, or written to, using the I
2
C bus. The ability to control writing to the register is provided
by the write protect (WP) input. The override (OVERRIDE) input forces all the register outputs to a low.
This device provides a fast-mode (400 kbit/s) or standard-mode (100 kbit/s) I
2
C serial interface for data input and
output. The implementation is as a slave. The device address is specified in the I
2
C interface definition table.
Both of the I
2
C Schmitt-trigger inputs (SCL and SDA) provide integrated pullup resistors and are 5-V tolerant.
The PCA8550 requires a monotonic power-supply ramp at start-up in the region of 1.1 V to 2.5 V. The
nonvolatile registers and I
2
C state machine initialize to their default states after this V
CC
level is passed.
The PCA8550 is characterized for operation from 0擄C to 70擄C.
ORDERING INFORMATION
T
A
SOIC 鈥?D
0擄C to 70擄C
SSOP 鈥?DB
TSSOP 鈥?PW
(1)
PACKAGE
(1)
Tube of 40
Reel of 2500
Reel of 2000
Reel of 2000
ORDERABLE PART NUMBER
PCA8550D
PCA8550DR
PCA8550DBR
PCA8550PWR
PCA8550
TOP-SIDE MARKING
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright 漏 1999鈥?005, Texas Instruments Incorporated

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