鈩?/div>
603e core microprocessor with a PCI bridge. The
PC8240鈥檚 PCI support will allow system designers to rapidly design systems using peripherals
already designed for PCI and the other standard interfaces. The PC8240 also integrates a high-
performance memory controller which supports various types of DRAM and ROM. The PC8240
is the first of a family of products that provides system level support for industry standard inter-
faces with a PowerPC microprocessor core.
The peripheral logic integrates a PCI bridge, memory controller, DMA controller, EPIC interrupt
controller, I
2
O controller, and a two-wire interface controller. The 603e core is a full-featured,
high-performance processor with floating-point support, memory management, 16-Kbyte
instruction cache, 16-Kbyte data cache, and power management features. The integration
reduces the overall packaging requirements and the number of discrete devices required for an
embedded system.
The PC8240 contains an internal peripheral logic bus that interfaces the 603e core to the
peripheral logic. The core can operate at a variety of frequencies, allowing the designer to trade
off performance for power consumption. The 603e core is clocked from a separate PLL, which
is referenced to the peripheral logic PLL. This allows the microprocessor and the peripheral
logic block to operate at different frequencies, while maintaining a synchronous bus interface.
The interface uses a 64- or 32-bit data bus (depending on memory data bus width) and a 32-bit
address bus along with control signals that enable the interface between the processor and
peripheral logic to be optimized for performance. PCI accesses to the PC8240鈥檚 memory space
are passed to the processor bus for snooping purposes when snoop mode is enabled.
The PC8240鈥檚 features serve a variety of embedded applications. In this way, the 603e core
and peripheral logic remain general-purpose. The PC8240 can be used as either a PCI host or
an agent controller.
Screening/Quality/Packaging
This product is manufactured in full compliance with:
鈥?/div>
Upscreening based upon Atmel standards
鈥?/div>
Industrial temperature range
(T
c
= -40擄C, T
c
= +110擄C)
(T
c
= -40擄C, T
c
= +125擄C): ZD3 suffix
鈥?/div>
鈥?/div>
鈥?/div>
Core power supply:
TP suffix
2.5 鹵 5 % V (L-Spec for 200 MHz)
I/O power supply: 3.0V to 3.6V
352 Tape Ball Grid Array (TBGA)
TBGA352
Tape Ball Grid Array
Rev. 2149A鈥揌IREL鈥?5/02
1
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