January 1998
PBL 388 13
Voice-switched Speakerphone Circuit
with built in loudspeaker amplifier
Description.
The PBL 388 13 contains all the necessary circuitry, amplifiers, detectors,
comparator and control functions to implement a high performance, voice-switched,
loudspeaking, 鈥漢ands-free 鈥?telephone. The gain dynamics (attenuation between
channels) is selectable (25dB or 50dB) via a separate pin. A background noise detector
in the transmitting channel reduces the influence of continuous external noise signals
to the switching .
The PBL 388 13 is designed for telephone systems that are either powered from
the telephone line or from a mains powered constant voltage dc. supply. The circuit
contains a transformerless audio power amplifier with a current supply circuitry
(patented) that eliminates the need of inductors. Automatic volume attenuation in the
power amplifier extends the operating range at low line currents. A special feature in
this circuit is that the power amplifier volume control can be implemented either as an
ac. potentiometer control or as a digital control by a
碌-processor
(dc. control).
Filtering is possible of both, the audio and the speech switching control signals,
in both transmitter and receiver channels.
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Key Features
Minimum of external components
needed for function.
Selectable gain dynamics. (25 or 50
dB)
Direct telephone line powered solution
(patented).
Low power consumption:
鈮?mA
at 3.3V
(typical) for speech switching, audio
power amplifier quiscent current
鈮?mA.
Drives an 25 - 50 ohm loudspeaker
without a transformer.
Background noise compensation in the
transmitting channel with hold function
at receive.
Input amplifiers of both channels have
balanced inputs.
Exellent noise performance.
Encapsulated in 24 pin plastic 鈥漵kinny鈥?/div>
DIP and 24 pin SO .
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
17
18
19
20
22
鈥?/div>
+
23
21
4
24
15
16
+
Control
F3
F6
12
10
P
B
L
3
11
8
8
PBL 388 13
1
3
24 pin SO
3
5
鈥?/div>
2
F1
+
7
6
8
9
1
Ref.
鈥?/div>
F4
13
+
14
P
B
L
F2
F5
3
8
24 pin DIP
Figure 1. Block diagram.
1
8
1
3
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