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PALCE29MA16 Datasheet

  • PALCE29MA16

  • 24-Pin EE CMOS Programmable Array Logic

  • 293.01KB

  • 25頁

  • AMD

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FINAL
COM鈥橪: H-25
PALCE29MA16H-25
24-Pin EE CMOS Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
s
High-performance semicustom logic
s
Register/Latch Preload permits full logic
s
s
s
s
s
s
replacement; Electrically Erasable (EE)
technology allows reprogrammability
16 bidirectional user-programmable I/O logic
macrocells for Combinatorial/Registered/
Latched operation
Output Enable controlled by a pin or product
terms
Varied product term distribution for increased
design flexibility
Programmable clock selection with common
pin clock/latch enable (LE) or individual
product term clock/LE with LOW/HIGH clock/
LE
polarity
s
s
verification
High speed (t
PD
= 25 ns, f
MAX
= 33 MHz and f
MAX
internal = 50 MHz)
Full-function AC and DC testing at the factory
for high programming and functional yields
and high reliability
24-pin 300 mil SKINNYDIP and 28-pin plastic
leaded chip carrier packages
Extensive third-party software and programmer
support through FusionPLD partners
GENERAL DESCRIPTION
The PALCE29MA16 is a high-speed, EE CMOS Pro-
grammable Array Logic (PAL) device designed for gen-
eral logic replacement in TTL or CMOS digital systems.
It offers high speed, low power consumption, high
programming yield, fast programming, and excellent
reliability. PAL devices combine the flexibility of custom
logic with the off-the-shelf availability of standard
products, providing major advantages over other
BLOCK DIAGRAM
CLK/LE
I/OF
7
I/OF
6
I/O
7
I/O
6
I/O
5
I/O
4
I/OF5
I/OF4
I/O
Logic
Macrocell
I/O
Logic
Macrocell
I/O
Logic
Macrocell
I/O
Logic
Macrocell
I/O
Logic
Macrocell
I/O
Logic
Macrocell
I/O
Logic
Macrocell
I/O
Logic
Macrocell
V
V
V
V
V
4
4
4
4
4
8
4
12
V
4
12
4
8
V
4
4
V
4
4
Programmable
AND Array
58x178
4
4
4
4
4
8
4
12
4
12
4
8
4
4
4
4
I/O
Logic
Macrocell
I/O
Logic
Macrocell
I/O
Logic
Macrocell
I/O
Logic
Macrocell
I/O
Logic
Macrocell
I/O
Logic
Macrocell
I/O
Logic
Macrocell
I/O
Logic
Macrocell
V
V
V
V
V
V
V
4
I 0 -I 3
I/OE
I/OF0
I/OF
1
I/O
0
I/O
1
I/O
2
V
I/O
3
I/OF 2
I/OF3
08811G-1
Publication#
08811
Rev.
G
Issue Date:
June 1993
Amendment
/0
2-349

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