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PALCE20V8H-10JC/4 Datasheet

  • PALCE20V8H-10JC/4

  • EE CMOS 24-Pin Universal Programmable Array Logic

  • 27頁(yè)

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COM'L: H-5/7/10/15/25, Q-10/15/25
IND: H-15/25, Q-20/25
PALCE20V8 Family
EE CMOS 24-Pin Universal
Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
x
Pin and function compatible with all PAL
廬
20V8 devices
x
Electrically erasable CMOS technology provides recon鏗乬urable logic and full testability
x
High-speed CMOS technology
x
x
x
x
x
x
x
x
x
x
x
鈥?5-ns propagation delay for 鈥?5鈥?version
鈥?7.5-ns propagation delay for 鈥?7鈥?version
Direct plug-in replacement for a wide range of 24-pin PAL devices
Programmable enable/disable control
Outputs individually programmable as registered or combinatorial
Peripheral Component Interconnect (PCI) compliant
Preloadable output registers for testability
Automatic register reset on power-up
Cost-effective 24-pin plastic SKINNY DIP and 28-pin PLCC packages
Extensive third-party software and programmer support
Fully tested for 100% programming and functional yields and high reliability
Programmable output polarity
5-ns version utilizes a split leadframe for improved performance
GENERAL DESCRIPTION
The PALCE20V8 is an advanced PAL device built with low-power, high-speed, electrically-
erasable CMOS technology. Its macrocells provide a universal device architecture. The
PALCE20V8 is fully compatible with the GAL20V8 and can directly replace PAL20R8 series
devices and most 24-pin combinatorial PAL devices.
Device logic is automatically con鏗乬ured according to the user鈥檚 design speci鏗乧ation. A design is
implemented using any of a number of popular design software packages, allowing automatic
creation of a programming 鏗乴e based on Boolean or state equations. Design software also veri鏗乪s
the design and can provide test vectors for the 鏗乶ished device. Programming can be
accomplished on standard PAL device programmers.
The PALCE20V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to
implement complex logic functions easily and ef鏗乧iently. Multiple levels of combinatorial logic
can always be reduced to sum-of-products form, taking advantage of the very wide input gates
available in PAL devices. The equations are programmed into the device through 鏗俹ating-gate
cells in the AND logic array that can be erased electrically.
Publication#
16491
Amendment/0
Rev:
E
Issue Date:
November 1998

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