USE ULTRA37000鈩?FOR
ALL NEW DESIGNS
PALCE16V8
Flash-Erasable Reprogrammable
CMOS PAL
廬
Device
Features
鈥?Active pull-up on data input pins
鈥?Low power version (16V8L)
鈥?55 mA max. commercial (10, 15, 25 ns)
鈥?65 mA max. industrial (10, 15, 25 ns)
鈥?65 mA military (15 and 25 ns)
鈥?Standard version has low power
鈥?90 mA max. commercial (10, 15, 25 ns)
鈥?115 mA max. commercial (7 ns)
鈥?130 mA max. military/industrial (10, 15, 25 ns)
鈥?CMOS Flash technology for electrical erasability and
reprogrammability
鈥?PCI-compliant
鈥?User-programmable macrocell
鈥?Output polarity control
鈥?Individually selectable for registered or combina-
torial operation
鈥?Up to 16 input terms and eight outputs
鈥?7.5 ns com鈥檒 version
5 ns t
CO
5 ns t
S
7.5 ns t
PD
125-MHz state machine
鈥?10 ns military/industrial versions
7 ns t
CO
10 ns t
S
10 ns t
PD
62-MHz state machine
鈥?High reliability
鈥?Proven Flash technology
鈥?100% programming and functional testing
Functional Description
The Cypress PALCE16V8 is a CMOS Flash Electrical
Erasable second-generation programmable array logic
device. It is implemented with the familiar sum-of-product
(AND-OR) logic structure and the programmable macrocell.
Logic Block Diagram (PDIP/CDIP)
GND
10
I
8
9
I
7
8
I
6
7
I
5
6
I
4
5
I
3
4
I
2
3
I
1
2
CLK/I
0
1
PROGRAMMABLE
AND ARRAY
(64 x 32)
8
8
8
8
8
8
8
8
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
11
OE/I
9
12
I/O
0
13
I/O
1
14
I/O
2
15
I/O
3
16
I/O
4
17
I/O
5
18
I/O
6
19
I/O
7
20
V
CC
Pin Configurations
CLK/I
0
I
1
I
2
I
3
I
4
I
5
I
6
I
7
I
8
GND
Cypress Semiconductor Corporation
Document #: 38-03025 Rev. *A
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
I
8
GND
OE/I
9
I/O
0
I/O
1
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
2
I/O
1
I/O
0
OE/I
9
I
3
I
4
I
5
I
6
I
7
I
2
I
1
0
V
CC
I/O
7
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10111213
I/O
6
I/O
5
I/O
4
I/O
3
I/O
2
DIP
Top View
PLCC/LCC
Top View
鈥?/div>
408-943-2600
Revised April 22, 2004
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