PA7572 PEEL Array鈩?/div>
Programmable Electrically Erasable Logic Array
Versatile Logic Array Architecture
- 24 I/Os, 14 inputs, 60 registers/latches
- Up to 72 logic cell output functions
- PLA structure with true product-term sharing
- Logic functions and registers can be I/O-buried
High-Speed Commercial and Industrial Versions
- As fast as 13ns/20ns (tpdi/tpdx), 66.6MHz (f
MAX
)
-
Industrial grade available for 4.5 to 5.5V V
CC
and -40
to +85 擄C temperatures
Ideal for Combinatorial, Synchronous and
Asynchronous Logic Applications
- Integration of multiple PLDs and random logic
- Buried counters, complex state-machines
- Comparators, decoders, other wide-gate functions
CMOS Electrically Erasable Technology
-
Reprogrammable in 40-pin DIP, 44-pin PLCC and
TQFP packages
Flexible Logic Cell
- Up to 3 output functions per logic cell
- D,T and JK registers with special features
- Independent or global clocks, resets, presets,
clock polarity and output enables
- Sum-of-products logic for output enables
Development and Programmer Support
- ICT PLACE Development Software
- Fitters for ABEL, CUPL and other software
- Programming support by popular third-party
programmers
General Description
The PA7572 is a member of the Programmable Electrically
Erasable Logic (PEEL鈩? Array family based on Anachip鈥檚
CMOS EEPROM technology. PEEL鈩?Arrays free
designers from the limitations of ordinary PLDs by
providing the architectural flexibility and speed needed for
today鈥檚 programmable logic designs. The PA7572 offers a
versatile logic array architecture with 24 I/O pins, 14 input
pins and 60 registers/latches (24 buried logic cells, 12 input
registers/latches, 24 buried I/O registers/latches). Its logic
array implements 100 sum-of-products logic functions
divided into two groups each serving 12 logic cells. Each
group shares half (60) of the 120 product-terms available.
The PA7572鈥檚 logic and I/O cells (LCCs, IOCs) are
extremely flexible with up to three output functions per cell
(a total of 72 for all 24 logic cells). Cells are configurable as
D, T, and JK registers with independent or global clocks,
resets, presets, clock polarity, and other features, making
the PA7572 suitable for a variety of combinatorial,
synchronous and asynchronous logic applications. The
PA7572 supports speeds as fast as 13ns/20ns (tpdi/tpdx)
and 66.6MHz (f
MAX
) at moderate power consumption
140mA (100mA typical). Packaging includes 40-pin DIP
and 44-pin PLCC (see Figure 1). Anachip and popular
third-party development tool manufacturers provide
development and programming support for the PA7572.
Figure 1. Pin Configuration
DIP (600 mil)
I/CLK1
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
G ND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I/CLK2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
G ND
I/O
I
I
I
I/CLK1
VCC
VCC
I
I
I
I/O
Figure 2. Block Diagram
2 Input/
G lobal Clock Pins
G ND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
6 5 4 3 2 1 44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
18 19 20 21 22 23 24 25 26 27 28
PLCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
G ND
7
8
9
10
11
12
13
14
15
16
17
G lobal
Ce lls
12 Input Pins
Input
Cells
(INC)
2
124 (62X2)
Array Inputs
true and
com plem ent
24
Buried
logic
Logic
func tions
to I/O cells
I/O
Cells
(IO C)
24 I/O Pins
12
I/CLK
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
Global C ells
VCC
I
I/O Cells
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I/CLK 2
24
Lo gic
A rray
I/O
I
I
I
I/CLK1
VCC
VCC
I
I
I/O
I
I
I/O
I
I
G ND
G ND
I/CLK2
I
I
I
I/O
Input Cells
A
B
C
D
Logic
Control
Cells
(LCC)
24
24
T Q FP
44 43 42 41 40 39 38 37 36 35 34
1
33
2
32
3
31
4
30
5
29
6
28
7
27
8
26
9
25
10
24
11
23
12 13 14 15 16 17 18 19 20 21 22
I/O
I
I
I
G ND
G ND
I/CLK2
I
I
I
I/O
G ND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
4 sum term s
5 product term s
for G lobal Cells
96 sum term s
(four per LCC)
24 Logic Control Cells
up to 3 output functions per cell
(72 total output functions
possible)
Logic C ontrol Cells
08-15-001A
GND
PA7572
08-15-002A
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights
under any patent accompany the sale of the product.
Rev. 1.0 Dec 16, 2004
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ANACHIP
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