Commercial/
Industrial
PA7024
PA7024 PEEL
TM
Array
Programmable Electrically Erasable Logic Array
Features
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CMOS Electrically Erasable Technology
- Reprogrammable in 24-pin DIP, SOIC and
28-pin PLCC packages
-Optional JN package for 22V10 power/ground
compatibility
Most Powerful 24-pin PLD Available
- 20 I/Os, 2 inputs/clocks, 40 registers/latches
- 40 logic cell output functions
- PLA structure with true product-term sharing
- Logic functions and registers can be I/O-buried
Flexible Logic Cell
- Multiple output functions per cell
- D,T and JK registers with special features
- Independent or global clocks, resets, presets,
clock polarity and output enables
-Sum of products logic for output enable
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High-Speed Commercial and Industrial Versions
- As fast as 10ns/15ns (tpdi/tpdx), 71.4MHz (fMAX)
- Industrial grade available for 4.5 to 5.5V Vcc
and -40 to +85擄C temperatures
Ideal for Combinatorial, Synchronous and
Asynchronous Logic Applications
- Integration of multiple PLDs and random logic
- Buried counters, complex state-machines
- Comparators, decoders, multiplexers and
other wide-gate functions
Development and Programmer Support
- ICT PLACE Development Software
- Fitters for ABEL, CUPL and other software
-Programming support by ICT PDS-3 and popular third-
party programmers
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General Description
The PA7024 is a member of the Programmable Electrically
Erasable Logic (PEEL鈩? Array family based on ICT鈥檚
CMOS EEPROM technology. PEEL鈩?Arrays free design-
ers from the limitations of ordinary PLDs by providing the
architectural flexibility and speed needed for today鈥檚 pro-
grammable logic designs. The PA7024 is by far the most
powerful 24-pin PLD available today with 20 I/O pins, 2
input/global-clocks and 40 registers/latches (20 buried logic
cells and 20 I/O registers/latches). Its logic array imple-
ments 84 sum-of-product logic functions that share 80
product terms. The PA7024鈥檚 logic and I/O cells (LCCs,
IOCs) are extremely flexible, offering two output functions
per logic cell (a total of 40 for all 20 logic cells). Logic cells
are configurable as D, T, and JK registers with independent
or global clocks, resets, presets, clock polarity, and other
special features. This makes them suitable for a wide vari-
ety of combinatorial, synchronous and asynchronous logic
applications. With pin compatibility and super-set function-
ality to most 24-pin PLDs, (22V10, EP610/630, GAL6002),
the PA7024 can implement designs that exceed the archi-
tectures of such devices. The PA7024 supports speeds as
fast as 10ns/15ns (tpdi/tpdx) and 71.4MHz (fMAX) at mod-
erate power consumption 120mA (85mA typical). Packag-
ing includes 24-pin DIP SOIC and 28-pin PLCC (see Figure
,
1). Development and programming support for the PA7024
is provided by ICT and popular third-party development tool
manufacturers.
Figure 1: Pin Configuration
Figure 2. Block Diagram
DIP
SOIC
PLCC-J
PLCC-JN
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