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P89LPC920FDH Datasheet

  • P89LPC920FDH

  • 8-bit microcontrollers with two-clock 80C51 core 2 kB/4 kB/8...

  • 45頁

  • PHILIPS

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P89LPC920/921/922
8-bit microcontrollers with two-clock 80C51 core
2 kB/4 kB/8 kB 3 V low-power Flash with 256-byte data RAM
Rev. 06 鈥?21 November 2003
Product data
1. General description
The P89LPC920/921/922 are single-chip microcontrollers designed for applications
demanding high-integration, low cost solutions over a wide range of performance
requirements. The P89LPC920/921/922 is based on a high performance processor
architecture that executes instructions in two to four clocks, six times the rate of
standard 80C51 devices. Many system-level functions have been incorporated into
the P89LPC920/921/922 in order to reduce component count, board space, and
system cost.
2. Features
2.1 Principal features
s
2 kB/4 kB/8 kB Flash code memory with 1 kB erasable sectors, 64-byte erasable
page size, and single byte erase.
s
256-byte RAM data memory.
s
Two 16-bit counter/timers. Each timer may be con鏗乬ured to toggle a port output
upon timer over鏗俹w or to become a PWM output.
s
Real-Time clock that can also be used as a system timer.
s
Two analog comparators with selectable inputs and reference source.
s
Enhanced UART with fractional baud rate generator, break detect, framing error
detection, automatic address detection and versatile interrupt capabilities.
s
400 kHz byte-wide I
2
C-bus communication port.
s
Con鏗乬urable on-chip oscillator with frequency range and RC oscillator options
(selected by user programmed Flash con鏗乬uration bits). The RC oscillator option
allows operation without external oscillator components. Oscillator options
support frequencies from 20 kHz to the maximum operating frequency of 12 MHz.
The RC oscillator option is selectable and 鏗乶e tunable.
s
2.4 V to 3.6 V V
DD
operating range. I/O pins are 5 V tolerant (may be pulled up or
driven to 5.5 V).
s
15 I/O pins minimum. Up to 18 I/O pins while using on-chip oscillator and reset
options.
2.2 Additional features
s
20-pin TSSOP and DIP packages.
s
A high performance 80C51 CPU provides instruction cycle times of 167 ns to
333 ns for all instructions except multiply and divide when executing at 12 MHz.
This is 6 times the performance of the standard 80C51 running at the same clock
frequency. A lower clock frequency for the same performance results in power
savings and reduced EMI.

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