P4C422
P4C422
ULTRA HIGH SPEED 256 x 4
STATIC CMOS RAM
FEATURES
High Speed (Equal Access and Cycle Times)
鈥?10/12/15/20/25/35 ns (Commercial)
鈥?15/20/25 /35 ns (Military)
CMOS for Low Power
鈥?495 mW Max. 鈥?10/12/15/20/25 (Commercial)
鈥?495 mW Max. 鈥?15/20/25/35 (Military)
Single 5V
鹵
10% Power Supply
Separate I/O
Fully TTL Compatible Inputs and Outputs
Resistant to single event upset and latchup
resulting from advanced process and design
improvements
Standard 22-pin 400 mil DIP, 24-pin 300 mil
SOIC, 24-pin LCC package and 24-pin CERPACK
package
DESCRIPTION
The P4C422 is a 1,024-bit high-speed (10ns) Static RAM
with a 256 x 4 organization. The memory requires no
clocks or refreshing and has equal access and cycle
times. Inputs and outputs are fully TTL compatible.
Operation is from a single 5 Volt supply. Easy memory
expansion is provided by an active LOW chip select one
(CS
1
) and active HIGH chip select two (CS
2
) as well as 3-
state outputs.
In addition to very high performance and very high den-
sity, the device features latch-up protection, single event
and upset protection. The P4C422 is offered in several
packages: 22-pin 400 mil DIP (plastic and ceramic), 24-
pin 300 mil SOIC, 24-pin LCC and 24-pin CERPACK.
Devices are offered in both commercial and military
temperature ranges.
FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATIONS
CS
2
CS
1
A3
A2
A1
A0
A5
A6
A7
GND
D0
O0
D1
NC
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V CC
A4
WE
CS
1
OE
CS 2
O3
D3
O2
D2
O1
NC
D
0
D
1
D
2
D
3
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
DATA INPUT
CONTROL
WE
OE
32 X 32
ARRAY
ROW
DECODER
SENSE AMPS
O
0
O
1
O
2
O
3
A3
A2
A1
A0
A5
A6
A7
GND
D0
O0
D1
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
18
17
16
15
14
13
12
V CC
A4
WE
CS
1
OE
CS 2
O3
D3
O2
D2
O1
INDEX
A1 A2 A3 VCC A4 WE
3
4
5
6
7
8
9
10
D0
11
O0
12
13
14
2
1
24
23
22
21
20
19
18
17
16
15
A0
A5
NC
A6
A7
GND
CS1
OE
CS2
NC
O3
D3
D1 O1
D 2 O2
COLUMN
DECODER
SOIC (S4)
CERPACK (F3) SIMILAR
TOP VIEW
DIP (P3-1, D3-1)
TOP VIEW
LCC (L4)
TOP VIEW
Means Quality, Service and Speed
1Q97
1