P4C1981/P4C1981L, P4C1982/P4C1982L
ULTRA HIGH SPEED 16K x 4
CMOS STATIC RAMS
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
鈥?10/12/15/20/25 ns (Commercial)
鈥?12/15/20/25/35 ns (Industrial)
鈥?15/20/25/35/45 ns (Military)
Low Power Operation (Commercial/Military)
鈥?715 mW Active 鈥?12/15
鈥?550/660 mW Active 鈥?20/25/35/45
鈥?193/220 mW Standby (TTL Input)
鈥?83/110 mW Standby (CMOS Input) P4C1981/1981L
鈥?5.5 mW Standby (CMOS Input)
P4C1981L/82L (Military)
Output Enable and Dual Chip Enable Functions
P4C1981/1981L, P4C1982/1982L
5V
鹵
10% Power Supply
Data Retention with 2.0V Supply, 10
碌
A Typical
Current (P4C1981L/1982L (Military)
Separate Inputs and Outputs
鈥?P4C1981/L Input Data at Outputs during Write
鈥?P4C1982/L Outputs in High Z during Write
Fully TTL Compatible Inputs and Outputs
Standard Pinout (JEDEC Approved)
鈥?28-Pin 300 mil DIP, SOJ
鈥?28-Pin 350 x 550 mil LCC
DESCRIPTION
The P4C1981/L and P4C1982/L are 65,536-bit (16Kx4)
ultra high-speed static RAMs similar to the P4C198, but
with separate data I/O pins. The P4C1981/L feature a
transparent write operation when
OE
is low; the outputs of
the P4C1982/L are in high impedance during the write
cycle. All devices have low power standby modes. The
RAMs operate from a single 5V
鹵
10% tolerance power
supply. With battery backup, data integrity is maintained
for supply voltages down to 2.0V. Current drain is typically
10
碌A
from 2.0V supply.
Access times as fast as 10 nanoseconds are available,
permitting greatly enhanced system operating speeds.
CMOS is used to reduce power consumption to a low 715
mW active, 193 mW standby. For the P4C1982L and
P4C1981L, power is only 5.5 mW standby with CMOS
input levels. The P4C1981/L and P4C1982/L are mem-
bers of a family of PACE RAM鈩?products offering fast
access times.
The P4C1981/L and P4C1982/L are available in 28-pin
300 mil DIP and SOJ, and in 28-pin 350x550 mil LCC
packages providing excellent board level densities.
FUNCTIONAL BLOCK DIAGRAM
A
(8)
A
I
1
I
2
I
3
I
4
O
1
O
2
O
3
O
4
ROW
SELECT
65,536-BIT
MEMORY
ARRAY
PIN CONFIGURATIONS
VCC
A 13
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
I
1
COLUMN
SELECT
INPUT
DATA
CONTROL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
A13
A 12
A11
A10
A9
I4
I3
A3
A4
A5
A6
A7
A8
I1
I2
CE
1
3
4
5
6
7
8
9
10
11
12
13
OE
A2
A1
A0
2
1
28
27
26
25
24
23
22
21
20
19
A12
A11
A10
A9
I4
I3
O4
O3
O2
COLUMN I/O
O4
O3
O2
O1
WE
CE
2
I
2
CE
1
OE
GND
14 15 16
GND
CE
2
18
17
CE
2
WE
OE
P4C1982
P4C1981
A
(6)
A
DIP (P5, D5-2), SOJ (J5)
TOP VIEW
P4C1981/ 1982
LCC (L5)
TOP VIEW
Means Quality, Service and Speed
1Q97
81
WE
O1
CE
1
1
2
3
4
5
6
7
8
9
10
