P4C174
P4C174
HIGH SPEED 8K x 8
CACHE TAG STATIC RAM
FEATURES
High Speed Address-To-Match - 8 ns Maximum
Access Time
High-Speed Read-Access Time
鈥?8/10/12/15/20/25 ns (Commercial)
Open Drain MATCH Output
Reset Function
8-Bit Tag Comparison Logic
Automatic Powerdown During Long Cycles
Data Retention at 2V for Battery Backup Operation
Advanced CMOS Technology
Low Power Operation
鈥?Active: 750 mW Typical at 25 ns
鈥?Standby: 500
碌W
Typical
Package Styles Available
鈥?28 Pin 300 mil Plastic DIP
鈥?28 Pin 300 mil Plastic SOJ
Single Power Supply
鈥?5V
鹵
10%
DESCRIPTION
The P4C174 is a 65,536 bit high speed cache tag static
RAM organized as 8K x 8. The CMOS memory has equal
access and cycle times. Inputs are fully TTL-compatible.
The cache tag RAMs operate from a single 5V鹵10%
power supply. An 8-bit data comparator with a MATCH
output is included for use as an address tag comparator in
high speed cache applications. The reset function pro-
vides the capability to reset all memory locations to a LOW
level.
The MATCH output of the P4C174 reflects the compari-
son result between the 8-bit data on the I/O pins and
the addressed memory location. 8K Cache lines can be
mapped into 1M-Byte address spaces by comparing 20
address bits organized as 13-line address bits and 7-page
address bits.
Low power operation of the P4C174 is enhanced by
automatic powerdown when the memory is deselected or
during long cycle times. Also, data retention is maintained
down to V
CC
= 2.0. Typical battery backup applications
consume only 30
碌
W at V
CC
=
3.0V.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
RESET
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
WE
MATCH
A
8
A
9
A
11
OE
A
10
CE
I/0
7
I/0
6
I/0
5
I/0
4
I/0
3
ROW
ADDRESS
8
ROW
SELECT
256 x 32 x 8
MEMORY
ARRAY
A
12
A
7
A
6
A
5
RESET
8
8
DATA
I/O
8
COMPARATOR
1 (IF MATCH)
A
4
COLUMN SELECT
& COLUMN
SENSE
8
5
COLUMN
ADDRESS
8
A
3
A
2
A
1
A
0
I/0
0
I/0
1
I/0
2
GND
WE
OE
CE
MATCH (OPEN DRAIN)
174.1
DIP (P5), SOJ (J5)
TOP VIEW
Means Quality, Service and Speed
1Q97
99