P4C1256L-12CMBLF Datasheet

IC型號：
P4C1256L-12CMBLF
PDF描述：
HIGH SPEED 32K x 8 STATIC CMOS RAM
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170.82KB
PDF頁數(shù)：
17頁
芯片廠家：
PYRAMID

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P4C1256

HIGH SPEED 32K x 8

STATIC CMOS RAM

FEATURES

High Speed (Equal Access and Cycle Times)

鈥?12/15/20/25/35 ns (Commercial)

鈥?15/20/25/35/45 ns (Industrial)

鈥?20/25/35/45/55/70 ns (Military)

Low Power

Single 5V鹵10% Power Supply

Easy Memory Expansion Using

and

Inputs

Common Data I/O

Three-State Outputs

Fully TTL Compatible Inputs and Outputs

Advanced CMOS Technology

Fast t

Automatic Power Down

Packages

鈥?8-Pin 300 mil DIP, SOJ, TSOP

鈥?8-Pin 300 mil Ceramic DIP

鈥?8-Pin 600 mil Ceramic DIP

鈥?8-Pin CERPACK

鈥?8-Pin SOP

鈥?8-Pin LCC (350 mil x 550 mil)

鈥?2-Pin LCC (450 mil x 550 mil)

DESCRIPTION

The P4C1256 is a 262,144-bit high-speed CMOS

static RAM organized as 32Kx8. The CMOS memory

requires no clocks or refreshing, and has equal access

and cycle times. Inputs are fully TTL-compatible. The

RAM operates from a single 5V鹵10% tolerance power

supply.

Access times as fast as 12 nanoseconds permit greatly

enhanced system operating speeds. CMOS is utilized

to reduce power consumption to a low level. The

P4C1256 is a member of a family of PACE RAM鈩?prod-

ucts offering fast access times.

The P4C1256 device provides asynchronous operation

with matching access and cycle times. Memory loca-

tions are specified on address pins A

to A

. Reading

is accomplished by device selection (CE and output

enabling (OE) while write enable (WE) remains HIGH.

By presenting the address under these conditions, the

data in the addressed memory location is presented on

the data input/output pins. The input/output pins stay

in the HIGH Z state when either

is HIGH or

is LOW.

Package options for the P4C1256 include 28-pin 300

mil DIP, SOJ and TSOP packages. For military tempera-

ture range, Ceramic DIP and LCC packages are avail-

able.

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATIONS

DIP (P5, C5, C5-1, D5-2), SOJ (J5), SOP (S11-1, S11-3)

CERPACK (F4) SIMILAR

1519B

See end of datasheet for LCC and TSOP

pin configurations.

Document #

SRAM119

REV G

Revised June 2007

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P4C1256L-12CMBLF Datasheet

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