P4C116
P4C116
ULTRA HIGH SPEED 2K x 8
STATIC CMOS RAMS
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
鈥?10/12/15/20/25/35 ns (Commercial)
鈥?15/20/25/35 ns (Military)
Low Power Operation
鈥?633/715 mW Active 鈥?15, 20
鈥?550/633 mW Active 鈥?25, 35
鈥?193/220 mW Standby (TTL Input)
Output Enable Control Function
Single 5V
鹵
10% Power Supply
Common Data I/O
Fully TTL Compatible Inputs and Outputs
Produced with PACE II Technology
TM
Standard Pinout (JEDEC Approved)
鈥?24-Pin 300 mil DIP, SOIC, SOJ
鈥?24-Pin Rectangular LCC (300 x 400 mils)
鈥?28-Pin Square LCC (450 x 450 mils)
DESCRIPTION
The P4C116 is a 16,384-bit ultra high-speed static RAMs
organized as 2K x 8. The CMOS memories require no
clocks or refreshing and have equal access and cycle
times. Inputs are fully TTL-compatible. The RAMs oper-
ate from a single 5V鹵10% tolerance power supply. Cur-
rent drain is typically 10
碌A
from a 2.0V supply.
Access times as fast as 10 nanoseconds are available,
permitting greatly enhanced system operating speeds.
CMOS is used to reduce power consumption to a low 633
mW active, 193 mW standby.
The P4C116 is available in 24-pin 300 mil DIP, SOJ and
SOIC packages providing excellent board level densities.
The P4C116 is also available in 24-pin rectangular and
28-pin square LCC packages.
FUNCTIONAL BLOCK DIAGRAM
A
(6)
A
I/O
1
INPUT
DATA
CONTROL
COLUMN I/O
ROW
SELECT
16,384-BIT
MEMORY
ARRAY
PIN CONFIGURATIONS
A0
A1
A2
A3
A4
A5
A6
A7
I/O 1
I/O 2
I/O 3
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V CC
A10
A9
WE
OE
A8
CE
I/O8
I/O7
I/O6
I/O5
I/O4
I/O
8
COLUMN
SELECT
WE
CE
OE
A
(5)
A
DIP (P4, D4), SOJ (J4), SOIC (S4)
DIP (P4 , D4), SOJ (J3 ), SOIC (S4 )
TOP VIEW
TOP VIEW
See Selection Guide Page for LCC
Means Quality, Service and Speed
1Q97
47
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