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P1753-40GMB Datasheet

  • P1753-40GMB

  • SINGLE CHIP, 40MHz CMOS MMU/COMBO

  • 21頁

  • PYRAMID

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PACE1753
SINGLE CHIP, 40MHz
CMOS MMU/COMBO
FEATURES
Implements the MIL-STD-1750A Instruction Set
Architecture for Memory Management and
Protection of up to 1 Megaword. All mapping
memory (10,240 bits) for both the MMU and
BPU functions are included on the chip.
Designed to interface memory to the
PACE1750A/AE 16-bit, 40 MHz processor.
Systems can be designed where no WAIT
states are required up to 40 MHz clock rates
when using these PACE products.
System performance and device count are
optimized when used with the PACE1754
Processor Interface Circuit (PIC).
Provides the following additional functions:
鈥?EDAC, Error Detection and Correction鈥攐r
parity generation and detection
鈥?Correct data register鈥攆or diagnostics
鈥?First memory failing address register
鈥?Illegal address error detection鈥?/div>
programmable
鈥?Multi-Master arbitration
8-bit extended address latches and drivers on
chip
Information bus and EDAC transceivers on chip
20, 30 and 40 MHz operation over the Military
Temperature Range
Single 5V 鹵 10% Power Supply
Power Dissipation over Military Temperature
Range (P
D
Outputs Open)
< 0.20 watts at 20 MHz
< 0.30 watts at 30 MHz
< 0.40 watts at 40 MHz
Available in:
鈥?64-Pin DIP or Gull Wing (50 Mil Pin centers)
鈥?68-Pin Pin Grid Array (PGA) (100 Mil centers)
鈥?68-Lead Quad Pack (Leaded Chip Carrier)
MEMORY MANAGEMENT UNIT AND
BLOCK PROTECT UNIT 鈥淐OMBO鈥?鈥?/div>
FUNCTIONAL DESCRIPTION
The PACE1753 (COMBO) is a support chip for the
PACE1750A/AE microprocessor family. It provides the
following supporting functions to the system:
1. Memory management and access protection for up
to 1M words.
2 Physical memory write protection for up to 1M words
memory in pages of 1K words each. Separate
protection is provided for the CPU and for DMA in
systems which include DMA.
3. Detection of illegal l/O accesses (as defined by MIL-
STD-1750A) or access to an unimplemented block
of memory. In each case an error flag is generated
to the processor.
4 Detection of double errors on the data bus and
correction of single errors. An error signal is generated
to the processor when a multiple error is detected.
5. RDYA generation. Up to three wait states can be
inserted in the address phase of the bus by generating
a not-ready, RDYA low signal. The number of wait
states required can be programmed in an internal
register in the COMBO.
6. Bus arbitration for up to 4 masters. Arbitration is
done on a fixed priority basis (i.e. by interconnection
of hardware). (In 68 pin package only).
Document #
MICRO-4
REV D
Revised November 2005

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