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P1750A-15QLMB Datasheet

  • P1750A-15QLMB

  • SINGLE CHIP, 15MHz to 40MHz, CMOS 16-BIT PROCESSOR

  • 24頁(yè)

  • PYRAMID

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PACE1750A
SINGLE CHIP, 15MHz to 40MHz,
CMOS 16-BIT PROCESSOR
FEATURES
Implements the MIL-STD-1750A Instruction Set
Architecture
Single Chip PACE Technology
TM
CMOS 16-Bit
Processor with 32 and 48-Bit Floating Point
Arithmetic
DAIS Instruction Mix Execution Performance
Including Floating Point Arithmetic
1.3 MIPS at 20 MHz
1.9 MIPS at 30 MHz
2.6 MIPS at 40 MHz
Integer DAIS Mix Performance
3.9 MIPS at 40 MHz
Conventional Integer Processing Mix
Performance
5.0 MIPS at 40 MHz
Instruction Execution at 40 MHz over the
Military Temperature Range
0.10 碌sec Integer Add/Sub
0.57 碌sec Integer Multiply
0.70 碌sec Floating Point Add/Sub
1.07 碌sec Floating Point Multiply
15, 20, 30, and 40 MHz Operation over the
Military Temperature Range
Extensive Error and Fault Management and
Interrupt Capability
24 User Accessible Registers
Single 5V 鹵 10% Power Supply
Power Dissipation over Military Temperature
Range
< 0.30 watts at 20 MHz
< 0.35 watts at 30 MHz
< 0.40 watts at 40 MHz
TTL Signal Level Compatible Inputs and
Outputs
Multiprocessor and Co-processor Capability
Built-In Function (BIF) for User Defined
Instructions
Two programmable Timers
Available in:
鈥?64-Pin DIP or Gull Wing (50 Mil Pin Centers)
鈥?68-Pin Pin Grid Array (PGA)
鈥?68-Lead Quad Pack (Leaded Chip Carrier)
GENERAL DESCRIPTION
The PACE1750A is a general purpose, single chip, 16-bit
CMOS microprocessor designed for high performance
floating point and integer arithmetic, with extensive real
time environment support. It offers a variety of data types,
including bits, bytes, 16-bit and 32-bit integers, and 32-bit
and 48-bit floating point numbers. It provides 13 addressing
modes, including direct, indirect, indexed, based, based
indexed and immediate long and short, and it can access
2 MWords of segmented memory space (64 KWords
segments).
The PACE1750A offers a well-rounded instruction set
with 130 instruction types, including a comprehensive
integer, floating point, integer-to-floating point and floating
point-to-integer set, a variety of stack manipulation
instructions, high level language support instructions
such as Compare Between Bounds and Loop Control
Instructions. It also offers some unique instructions such
as vectored l/O, supports executive and user modes, and
provides an escape mechanism which allows user-defined
instructions using a coprocessor.
The chip includes 16 general purpose registers, 8 other
user-accessible registers, and an array of real time
application support resources, such as 2 programmable
timers, a complete interrupt controller supporting 16
levels of prioritized internal and external interrupts, and a
faults and exceptions handler controlling internally and
externally generated faults.
The microprocessor achieves very high throughput of 2.6
MIPS for a standard real time integer/floating point
instruction mix at a 40 MHz clock. It executes integer Add
in 0.1 碌s, integer Multiply in 0.575 碌s, Floating Point Add
in 0.7 碌s, and Floating Point Multiply in 1.075 碌s, for
register operands at a 40 MHz clock speed.
The PACE1750A uses a single multiplexed 16-bit parallel
bus. Status signals are provided to determine whether
the processor is in the memory or I/O bus cycle, reading
and writing, and whether the bus cycle is for data or
instructions.
The basic bus cycle is 4 clocks long. The PACE1750A will
extend the cycle by insertion of wait states in the address
and data phases (in response to RDYA and RDYD
signals, repectively) and will hold the machine in HI-Z if
this CPU has not acquired the bus. A typical non-bus
cycle is three clocks long. However, variable length
cycles are used for such repetitive operations as multiply,
divide, scale and normalize, reducing significantly the
number of CPU CLOCKS per operation step and resulting
in very fast integer and floating point execution times.
Document #
MICRO-3
Rev. C
Revised October 2005

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