鈻?/div>
Traditional I/O selections:
鈥?LVTTL and LVCMOS (3.3 V, 2.5 V, and 1.8 V)
I/Os.
鈥?Per pin-selectable I/O clamping diodes provide
3.3 V PCI compliance.
鈥?Individually programmable drive capability:
24 mA sink/12 mA source, 12 mA sink/6 mA
source, or 6 mA sink/3 mA source.
鈥?Two slew rates supported (fast and slew-lim-
ited).
鈥?Fast-capture input latch and input 鏗俰p-鏗俹p
(FF)/latch for reduced input setup time and zero
hold time.
鈥?Fast open-drain drive capability.
鈥?Capability to register 3-state enable signal.
鈥?Off-chip clock drive capability.
鈥?Two-input function generator in output path.
New programmable high-speed I/O:
鈥?Single-ended: GTL, GTL+, PECL, SSTL3/2
(class I and II), HSTL (Class I, III, and IV), ZBT,
and DDR.
鈥?Double-ended: LDVS, bused-LVDS, and
LVPECL. Programmable (on/off) internal parallel
termination (100
鈩?
also supported for these
I/Os.
Programmable Features
鈻?/div>
High-performance platform design:
鈥?0.16 碌m 7-level metal technology.
鈥?Internal performance of >250 MHz.
鈥?I/O performance of >420 MHz.
鈥?Meets multiple I/O interface standards.
鈥?1.5 V operation (30% less power than 1.8 V
operation) translates to greater performance.
Table 1.
ORCA
Series 4鈥擜vailable FPGA Logic
Device
OR4E2
OR4E4
OR4E6
Rows
26
36
46
Columns
24
36
44
PFUs
624
1296
2024
User I/O
400
576
720
LUTs
4,992
10,368
16,192
EBR
Blocks
8
12
16
EBR Bits
(K)
74
111
147
Usable*
Gates (K)
260鈥?15
380鈥?00
515鈥?095
* The usable gate counts range from a logic-only gate count to a gate count assuming 20% of the PFUs/SLICs being used as RAMs. The
logic-only gate count includes each PFU/SLIC (counted as 108 gates/PFU), including 12 gates per LUT/FF pair (eight per PFU) and
12 gates per SLIC/FF pair (one per PFU). Each of the four PIO groups are counted as 16 gates (three FFs, fast-capture latch, output
logic, CLK, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing a 32 x 4 RAM
(or 512 gates) per PFU. Embedded block RAM (EBR) is counted as four gates per bit, plus each block has an additional 25 K gates.
7 K gates are used for each PLL and 50K gates for the embedded system bus and microprocessor interface logic. Both the EBR and
PLLs are conservatively utilized in the gate count calculations.
Note: Devices are not pinout compatible with
ORCA
Series 2/3.
1
2
3
4
5
6
