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OP227AYMDA Datasheet

  • OP227AYMDA

  • Dual, Low Noise, Low Offset Instrumentation Operational Ampl...

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a
Dual, Low Noise, Low Offset
Instrumentation Operational Amplifier
OP227
PIN CONNECTIONS
NULL (A)
NULL (A)
鈥揑N (A)
+IN (A)
V鈥?(B)
OUT (B)
V+ (B)
1
2
3
14
13
12
FEATURES
Excellent Individual Amplifier Parameters
Low V
OS
, 80 V Max
Offset Voltage Match, 80 V Max
Offset Voltage Match vs. Temperature, 1 V/ C Max
Stable V
OS
vs. Time, 1 V/M
O
Max
Low Voltage Noise, 3.9 nV/梅Hz Max
Fast, 2.8 V/ s Typ
High Gain, 1.8 Million Typ
High Channel Separation, 154 dB Typ
V+ (A)
OUT (A)
V鈥?(A)
+IN (B)
鈥揑N (B)
NULL (B)
NULL (B)
A
4
11
B
5
6
7
10
9
8
NOTE
1. DEVICE MAY BE OPERATED EVEN IF INSERTION
IS REVERSED; THIS IS DUE TO INHERENT SYMMETRY
OF PIN LOCATIONS OF AMPLIFIERS A AND B
2. V鈥?A) AND V鈥?B) ARE INTERNALLY CONNECTED VIA
SUBSTRATE RESISTANCE
GENERAL DESCRIPTION
The OP227 is the first dual amplifier to offer a combination of
low offset, low noise, high speed, and guaranteed amplifier matching
characteristics in one device. The OP227, with a V
OS
match of
25
mV
typical, a TCV
OS
match of 0.3
mV/鈭濩
typical and a 1/f corner
of only 2.7 Hz is an excellent choice for precision low noise designs.
These dc characteristics, coupled with a slew rate of 2.8 V/ms
typical and a small-signal bandwidth of 8 MHz typical, allow the
designer to achieve ac performance previously unattainable with
op amp based instrumentation designs.
When used in a three op amp instrumentation configuration, the
OP227 can achieve a CMRR in excess of 100 dB at 10 kHz. In
addition, this device has an open-loop gain of 1.5 M typical with
a 1 kW load. The OP227 also features an I
B
of
鹵
10 nA typical,
an I
OS
of 7 nA typical, and guaranteed matching of input currents
between amplifiers. These outstanding input current specifications
are realized through the use of a unique input current cancellation
circuit which typically holds I
B
and I
OS
to
鹵
20 nA and 15 nA
respectively over the full military temperature range.
Other sources of input referred errors, such as PSRR and CMRR,
are reduced by factors in excess of 120 dB for the individual
amplifiers. DC stability is assured by a long-term drift application
of 1.0
mV/month.
Matching between channels is provided on all critical param-
eters including offset voltage, tracking of offset voltage versus
temperature, noninverting bias current, CMRR, and power
supply rejection ratio. This unique dual amplifier allows the
elimination of external components for offset nulling and
frequency compensation.
SIMPLIFIED SCHEMATIC
V+
Q6
R3
NULL
R1
*
R2
*
Q21
Q23
R23
R24
Q24
R4
C2
Q22
C1
Q20 Q19
R9
OUTPUT
NON
INVERTING
INPUT (+)
INVERTING
INPUT (鈥?
Q3
Q11
Q12
Q26
R12
Q1A Q1B
Q2B
Q2A
R5
C3
R11 C4
Q45
Q46
Q27
Q28
V-
*
R1 AND R2 ARE PREMATURELY ADJUSTED AT WAFER TEST FOR MINIMUM OFFSET VOLTAGE.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
漏 Analog Devices, Inc., 2002

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