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NZ48F000BTY Datasheet

  • NZ48F000BTY

  • StrataFlash Wireless Memory

  • 106頁

  • INTEL   INTEL

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Intel StrataFlash廬 Wireless Memory
(L18)
28F640L18, 28F128L18, 28F256L18
Datasheet
Product Features
High performance Read-While-Write/Erase
鈥?85 ns initial access
鈥?54 MHz with zero wait state, 14 ns clock-to-
data output synchronous-burst mode
鈥?25 ns asynchronous-page mode
鈥?4-, 8-, 16-, and continuous-word burst mode
鈥?Burst suspend
鈥?Programmable WAIT configuration
鈥?Buffered Enhanced Factory Programming
(BEFP) at 5 碌s/byte (Typ)
鈥?1.8 V low-power buffered programming at
7 碌s/byte (Typ)
鈻?/div>
Architecture
鈥?Asymmetrically-blocked architecture
鈥?Multiple 8-Mbit partitions: 64-Mbit and 128-
Mbit devices
鈥?Multiple 16-Mbit partitions: 256-Mbit devices
鈥?Four 16-Kword parameter blocks: top or
bottom configurations
鈥?64-Kword main blocks
鈥?Dual-operation: Read-While-Write (RWW) or
Read-While-Erase (RWE)
鈥?Status Register for partition and device status
鈻?/div>
Power
鈥?V
CC
(core) = 1.7 V - 2.0 V
鈥?V
CCQ
(I/O) = 1.35 V - 2.0 V, 1.7 V - 2.0 V
鈥?Standby current: 30 碌A(chǔ) (Typ) for 256-Mbit
鈥?4-Word synchronous read current: 15 mA (Typ)
at 54 MHz
鈥?Automatic Power Savings mode
鈻?/div>
Security
鈥?OTP space:
鈥?64 unique factory device identifier bits
鈥?64 user-programmable OTP bits
鈥?Additional 2048 user-programmable OTP bits
鈥?Absolute write protection: V
PP
= GND
鈥?Power-transition erase/program lockout
鈥?Individual zero-latency block locking
鈥?Individual block lock-down
鈻?/div>
Software
鈥?20 碌s (Typ) program suspend
鈥?20 碌s (Typ) erase suspend
鈥?Intel廬 Flash Data Integrator optimized
鈥?Basic Command Set (BCS) and Extended
Command Set (ECS) compatible
鈥?Common Flash Interface (CFI) capable
鈻?/div>
Quality and Reliability
鈥?Expanded temperature: 鈥?5擄 C to +85擄 C
鈥?Minimum 100,000 erase cycles per block
鈥?ETOX鈩?VIII process technology (0.13 碌m)
鈻?/div>
Density and Packaging
鈥?64-, 128-, and 256-Mbit density in VF BGA
packages
鈥?128/0 and 256/0 density in SCSP
鈥?16-bit wide data bus
鈻?/div>
The Intel StrataFlash
廬
wireless memory (L18) device is the latest generation of Intel
StrataFlash
廬
memory devices featuring flexible, multiple-partition, dual operation. It provides
high performance synchronous-burst read mode and asynchronous read mode using 1.8 V low-
voltage, multi-level cell (MLC) technology.
The multiple-partition architecture enables background programming or erasing to occur in one
partition while code execution or data reads take place in another partition. This dual-operation
architecture also allows a system to interleave code operations while program and erase
operations take place in the background. The 8-Mbit or 16-Mbit partitions allow system
designers to choose the size of the code and data segments. The L18 wireless memory device is
manufactured using Intel 0.13 碌m ETOX鈩?VIII process technology. It is available in industry-
standard chip scale packaging.
Order Number: 251902, Revision: 009
April 2005

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