NTE859/NTE859SM
Integrated Circuit
Quad, Low Noise, JFET Input
Operational Amplifier
Description:
The NTE859 (14鈥揕ead DIP) and NTE859SM (SOIC鈥?4 Surface Mount) JFET鈥搃nput operational am-
plifiers are low noise amplifiers with low noise input bias, offset currents, and fast slew rate. The low
harmonic distortion and low noise make these devices ideally suited as amplifiers for high鈥揻idelity and
audio preamplifier applications. Each amplifier features JFET鈥搃nputs (for high input impedance)
coupled with bipolar output stages all integrated on a single monolithic chip.
Features:
D
Low Power Consumption
D
Wide Common鈥揗ode and Differential Voltage Ranges
D
Low Input Bias and Offset Currents
D
Output Short鈥揅ircuit Protection
D
Low Total Harmonic Distortion: 0.003% Typ
D
Low Noise: Vn = 18nV鈭欻
Z
Typ
D
High Input Impedance: JFET鈥揑nput Stage
D
Internal Frequency Compensation
D
Latch鈥揢p Free Operation
D
High Slew Rate: 13V/碌s Typ
Absolute Maximum Ratings:
(T
A
= 0 to +70擄C unless otherwise specified)
Supply Voltage (Note 1), V
CC
(+) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18V
Supply Voltage (Note1), V
CC
(鈥? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 鈥?8V
Differential Input Voltage (Note 2), V
ID
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
鹵30V
Input Voltage Range (Note 1, Note 3),V
IDR
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
鹵15V
Duration of Output Short Circuit (Note 4),t
S
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited
Power Dissipation (T
A
= +25擄C), P
D
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680mW
Derate Above 25擄C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mW/擄C
Operating Ambient Temperature Range, T
A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0擄 to +70擄C
Storage Temperature Range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 鈥?5擄 to +150擄C
Lead Temperature (During Soldering, 1/16鈥?from Case for 10sec), T
L
. . . . . . . . . . . . . . . . . . +260擄C
Note 1. All voltage values, except differential voltages, are with reapect to the midpoint between
V
CC
(+) and V
CC
(鈥?.
Note 2. Differential voltages are at the non鈥搃nverting input pin with respect to the inverting pin.
Note 3. The magnitude of the input voltage must never exceed the magnitude of the supply voltage
or 15V, whichever is less.
Note 4. The output may be shorted to GND or to either supply. Temperature and/or supply voltages
must be limited to ensure that the dissipation rating is not exceeded.
1
2
3
