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NTD25P03LT4 Datasheet

  • NTD25P03LT4

  • Power MOSFET

  • 10頁

  • ONSEMI

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NTD25P03L
Power MOSFET
鈭?5 A, 鈭?0 V, Logic Level P鈭扖hannel
DPAK
Designed for low voltage, high speed switching applications and to
withstand high energy in the avalanche and commutation modes. The
source鈭抰o鈭抎rain diode recovery time is comparable to a discrete fast
recovery diode.
Typical Applications
V
(BR)DSS
鈭?0 V
http://onsemi.com
R
DS(on)
TYP
51 mW @ 5.0 V
D
I
D
MAX
鈭?5 A
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
PWM Motor Controls
Power Supplies
Converters
Bridge Circuits
Pb鈭扚ree Package is Available
P鈭扖hannel
G
MAXIMUM RATINGS
(T
J
= 25擄C unless otherwise noted)
Rating
Drain鈭抰o鈭扴ource Voltage
Gate鈭抰o鈭扴ource Voltage
鈭?Continuous
鈭?Non鈭扲epetitive (tp
鈮?/div>
10 ms)
Drain Current
鈭?Continuous @ T
A
= 25擄C
鈭?Single Pulse (t
p
鈮?/div>
10
ms)
Total Power Dissipation @ T
A
= 25擄C
Operating and Storage Temperature
Range
Single Pulse Drain鈭抰o鈭扴ource Avalanche
Energy 鈭?Starting T
J
= 25擄C
(V
DD
= 25 Vdc, V
GS
= 5.0 Vdc,
Peak I
L
= 20 Apk, L = 1.0 mH,
R
G
= 25
W)
Thermal Resistance
鈭?Junction鈭抰o鈭扖ase
鈭?Junction鈭抰o鈭扐mbient (Note 1)
鈭?Junction鈭抰o鈭扐mbient (Note 2)
Maximum Lead Temperature for Soldering
Purposes, (1/8鈥?from case for 10 s)
Symbol
V
DSS
V
GS
V
GSM
I
D
I
DM
P
D
T
J
, T
stg
E
AS
Value
鈭?0
"15
"20
鈭?5
鈭?5
75
鈭?5 to
+150
200
Unit
V
V
Vpk
A
Apk
Watts
擄C
mJ
1 2
3
DPAK
CASE 369C
(Surface Mount)
Style 2
4
YWW
25P
03L
2
1
3
Drain
Gate
Source
4
Drain
1
擄C/W
R
qJC
R
qJA
R
qJA
T
L
1.65
67
120
260
擄C
YWW
25P
03L
1 2 3
Gate Drain Source
Shipping
鈥?/div>
75 Units/Rail
75 Units/Rail
75 Units/Rail
2500/Tape & Reel
Publication Order Number:
NTD25P03L/D
Package
DPAK
DPAK
(Pb鈭扚ree)
DPAK
Straight Lead
DPAK
4
S
MARKING DIAGRAMS
4
Drain
3
DPAK
CASE 369D
(Straight Lead)
Style 2
25P03L
Device Code
Y
= Year
WW
= Work Week
2
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. When surface mounted to an FR4 board using 0.5 sq in pad size.
2. When surface mounted to an FR4 board using the minimum recommended
pad size.
ORDERING INFORMATION
Device
NTD25P03L
NTD25P03LG
NTD25P03L1
NTD25P03LT4
鈥燜or information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
漏
Semiconductor Components Industries, LLC, 2004
1
August, 2004 鈭?Rev. 1

NTD25P03LT4 產(chǎn)品屬性

  • 2,500

  • 分離式半導體產(chǎn)品

  • FET - 單

  • -

  • MOSFET P 通道，金屬氧化物

  • 邏輯電平門

  • 30V

  • 25A

  • 80 毫歐 @ 25A，5V

  • 2V @ 250µA

  • 20nC @ 5V

  • 1260pF @ 25V

  • 75W

  • 表面貼裝

  • TO-252-3，DPak（2 引線+接片），SC-63

  • DPAK-3

  • 帶卷 (TR)

  • NTD25P03LT4OS

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