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NTD18N06LT4 Datasheet

  • NTD18N06LT4

  • Power MOSFET

  • 8頁(yè)

  • ONSEMI

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NTD18N06L
Power MOSFET
18 Amps, 60 Volts, Logic Level
N鈭扖hannel DPAK
Designed for low voltage, high speed switching applications in
power supplies, converters and power motor controls and bridge
circuits.
Features
V
(BR)DSS
60 V
http://onsemi.com
R
DS(on)
TYP
54 mW@5.0 V
I
D
MAX
18 A
(Note 1)
鈥?/div>
Pb鈭扚ree Packages are Available
Typical Applications
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Power Supplies
Converters
Power Motor Controls
Bridge Circuits
G
N鈭扖hannel
D
MAXIMUM RATINGS
(T
J
= 25擄C unless otherwise noted)
Rating
Drain鈭抰o鈭扴ource Voltage
Drain鈭抰o鈭扜ate Voltage (R
GS
= 10 MW)
Gate鈭抰o鈭扴ource Voltage
鈭?Continuous
鈭?Non鈭抮epetitive (t
p
v10
ms)
Drain Current
鈭?Continuous @ T
A
= 25擄C
鈭?Continuous @ T
A
= 100擄C
鈭?Single Pulse (t
p
v10
ms)
Total Power Dissipation @ T
A
= 25擄C
Derate above 25擄C
Total Power Dissipation @ T
A
= 25擄C (Note 2)
Operating and Storage Temperature Range
Single Pulse Drain鈭抰o鈭扴ource Avalanche
Energy 鈭?Starting T
J
= 25擄C
(V
DD
= 50 Vdc, V
GS
= 5.0 Vdc,
L = 1.0 mH, I
L
(pk) = 12 A, V
DS
= 60 Vdc)
Thermal Resistance
鈭?Junction鈭抰o鈭扖ase
鈭?Junction鈭抰o鈭扐mbient (Note 1)
鈭?Junction鈭抰o鈭扐mbient (Note 2)
Maximum Lead Temperature for Soldering
Purposes, 1/8鈥?from case for 10 seconds
Symbol
V
DSS
V
DGR
V
GS
V
GS
I
D
I
D
I
DM
P
D
Value
60
60
"15
"20
4
18
10
54
55
0.36
2.1
鈭?5 to
+175
72
Adc
Apk
W
W/擄C
W
擄C
mJ
4
DPAK鈭?
CASE 369D
STYLE 2
擄C/W
R
qJC
R
qJA
R
qJA
T
L
2.73
100
71.4
260
擄C
18N6L
A
Y
WW
1
2
3
1 2 3
Gate Drain Source
Device Code
= Assembly Location
= Year
= Work Week
AYWW
18N6L
1 2
3
2
1
3
Drain
Gate
Source
4
Drain
DPAK
CASE 369C
STYLE 2
Unit
Vdc
Vdc
Vdc
S
MARKING
DIAGRAMS
4
Drain
AYWW
18N6L
T
J
, T
stg
E
AS
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits
are exceeded, device functional operation is not implied, damage may occur
and reliability may be affected.
1. When surface mounted to an FR鈭? board using the minimum recommended
pad size.
2. When surface mounted to an FR鈭? board using the 0.5 sq in drain pad size.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
漏
Semiconductor Components Industries, LLC, 2004
1
August, 2004 鈭?Rev. 3
Publication Order Number:
NTD18N06L/D

NTD18N06LT4 產(chǎn)品屬性

  • 2,500

  • 分離式半導(dǎo)體產(chǎn)品

  • FET - 單

  • -

  • MOSFET N 通道，金屬氧化物

  • 邏輯電平門(mén)

  • 60V

  • 18A

  • 65 毫歐 @ 9A，5V

  • 2V @ 250µA

  • 22nC @ 5V

  • 675pF @ 25V

  • 55W

  • 表面貼裝

  • TO-252-3，DPak（2 引線+接片），SC-63

  • DPAK-3

  • 帶卷 (TR)

  • NTD18N06LT4OS

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