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NTD110N02RT4 Datasheet

  • NTD110N02RT4

  • Power MOSFET

  • 67.81KB

  • 8頁(yè)

  • ONSEMI

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NTD110N02R
Power MOSFET
24 V, 110 A, N鈭扖hannel DPAK
Features
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Planar HD3e Process for Fast Switching Performance
Low R
DS(on)
to Minimize Conduction Loss
Low C
iss
to Minimize Driver Loss
Low Gate Charge
Optimized for High Side Switching Requirements in
High鈭扙fficiency DC鈭扗C Converters
鈥?/div>
Pb鈭扚ree Packages are Available
MAXIMUM RATINGS
(T
J
= 25擄C unless otherwise noted)
Rating
Drain鈭抰o鈭扴ource Voltage
Gate鈭抰o鈭扴ource Voltage 鈭?Continuous
Thermal Resistance 鈭?Junction鈭抰o鈭扖ase
Total Power Dissipation @ T
C
= 25擄C
Drain Current
鈭?Continuous @ T
C
= 25擄C, Chip
鈭?Continuous @ T
C
= 25擄C,
Limited by Package
鈭?Continuous @ T
A
= 25擄C,
Limited by Wires
鈭?Single Pulse (t
p
= 10
ms)
Thermal Resistance
鈭?Junction鈭抰o鈭扐mbient (Note 1)
鈭?Total Power Dissipation @ T
A
= 25擄C
鈭?Drain Current 鈭?Continuous @ T
A
= 25擄C
Thermal Resistance
鈭?Junction鈭抰o鈭扐mbient (Note 2)
鈭?Total Power Dissipation @ T
A
= 25擄C
鈭?Drain Current 鈭?Continuous @ T
A
= 25擄C
Operating and Storage
Temperature Range
Single Pulse Drain鈭抰o鈭扴ource Avalanche
Energy 鈭?Starting T
J
= 25擄C
(V
DD
= 50 Vdc, V
GS
= 10 Vdc,
I
L
= 15.5 Apk, L = 1.0 mH, R
G
= 25
W)
Maximum Lead Temperature for Soldering
Purposes, (1/8鈥?from case for 10 s)
Symbol
V
DSS
V
GS
R
qJC
P
D
I
D
I
D
I
D
I
D
R
qJA
P
D
I
D
R
qJA
P
D
I
D
T
J
, T
stg
E
AS
Value
24
鹵20
1.35
110
110
110
32
110
52
2.88
17.5
100
1.5
12.5
鈭?5 to
175
120
Unit
V
V
擄C/W
W
A
A
A
A
擄C/W
W
A
擄C/W
W
A
擄C
mJ
http://onsemi.com
V
(BR)DSS
24 V
R
DS(on)
TYP
4.1 mW @ 10 V
I
D
MAX
110 A
N鈭扖hannel
D
G
S
4
4
1 2
3
CASE 369AA
DPAK
(Surface Mount)
STYLE 2
1
2
3
CASE 369D
DPAK
(Straight Lead)
STYLE 2
MARKING DIAGRAM
& PIN ASSIGNMENTS
4
Drain
YWW
T
110N2
4
Drain
YWW
T
110N2
1 2 3
Gate Drain Source
= Year
= Work Week
= Device Code
Publication Order Number:
NTD110N02R/D
T
L
260
擄C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. When surface mounted to an FR4 board using 0.5 sq in drain pad size.
2. When surface mounted to an FR4 board using the minimum recommended
pad size.
2
1
3
Drain
Gate
Source
Y
WW
T110N2
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
漏
Semiconductor Components Industries, LLC, 2004
1
December, 2004 鈭?Rev. 6

NTD110N02RT4 產(chǎn)品屬性

  • 2,500

  • 分離式半導(dǎo)體產(chǎn)品

  • FET - 單

  • -

  • MOSFET N 通道，金屬氧化物

  • 邏輯電平門(mén)

  • 24V

  • 12.5A

  • 4.6 毫歐 @ 20A，10V

  • 2V @ 250µA

  • 28nC @ 4.5V

  • 3440pF @ 20V

  • 1.5W

  • 表面貼裝

  • TO-252-3，DPak（2 引線+接片），SC-63

  • D-Pak

  • 帶卷 (TR)

  • NTD110N02RT4OSTR

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