鈥?/div>
Planar HD3e Process for Fast Switching Performance
Low R
DS(on)
to Minimize Conduction Loss
Low C
iss
to Minimize Driver Loss
Low Gate Charge
Optimized for High Side Switching Requirements in
High鈭扙fficiency DC鈭扗C Converters
G
S
MAXIMUM RATINGS
(T
J
= 25擄C unless otherwise specified)
Parameter
Drain鈭抰o鈭扴ource Voltage
Gate鈭抰o鈭扴ource Voltage 鈭?Continuous
Drain Current
鈭?Continuous @ T
A
= 25擄C, Limited by Chip
鈭?Continuous @ T
A
= 25擄C, Limited by Package
鈭?Single Pulse (t
p
= 10
ms)
Total Power Dissipation @ T
A
= 25擄C
Operating and Storage Temperature Range
Thermal Resistance 鈭?Junction鈭抰o鈭扖ase
Maximum Lead Temperature for Soldering
Purposes, 1/8鈥?from case for 10 seconds
Symbol
V
DSS
V
GS
I
D
I
D
I
DM
P
D
T
J
, T
stg
R
qJC
T
L
Value
25
鹵20
23
6.0
60
37.5
鈭?5 to
150
3.3
260
W
擄C
擄C/W
擄C
Unit
Vdc
Vdc
A
1
2
3
D
2
PAK
CASE 418B
STYLE 2
T23N03
A
Y
WW
G
1
Gate
4
4 Drain
T23
N03G
AYWW
2
Drain
3
Source
MARKING DIAGRAM
& PIN ASSIGNMENTS
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb鈭扚ree Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
漏
Semiconductor Components Industries, LLC, 2005
1
August, 2005 鈭?Rev. 2
Publication Order Number:
NTB23N03R/D