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NT128D64S88A0G-8B Datasheet

  • NT128D64S88A0G-8B

  • 184pin One Bank Unbuffered DDR SDRAM MODULE

  • 193.83KB

  • 15頁(yè)

  • ETC

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NT128D64S88A0G
128MB : 16M x 64
PC2100 / PC1600 Unbuffered DIMM
184pin One Bank Unbuffered DDR SDRAM MODULE
Based on DDR266/200 16Mx8 SDRAM
Features
鈥?184-Pin Unbuffered 8-Byte Dual In-Line Memory Module
鈥?16Mx64 Double Data Rate (DDR) SDRAM DIMM
(16M X 8 SDRA MS)
鈥?Performance :
Speed Sort
DIMM
CAS
Latency
f
CK
Clock Frequency
t
CK
Clock Cycle
PC1600
- 8B
2
100
10
PC2100
- 75B
- 7K
2.5
133
7.5
2
133
7.5
MHz
ns
Unit
鈥?Data is read or written on both clock edges
鈥?DRAM D
LL
aligns DQ and DQS transitions with clock transitions.
Also aligns QFC transitions with clock during Read cycles
鈥?Address and control signals are fully synchronous to positive
clock edge
鈥?Programmable Operation:
- DIMM
CAS
Latency: 2, 2.5
- Burst Type: Sequential or Interleave
- Burst Length: 2, 4, 8
- Operation: Burst Read and Write
鈥?Auto Refresh (CBR) and Self Refresh Modes
鈥?Automatic and controlled precharge commands
鈥?12/10/2 Addressing (row/column/bank)
鈥?15.6 碌s Max. Average Periodic Refresh Interval
鈥?Serial Presence Detect
鈥?Gold contacts
鈥?SDRAMs in 66-pin TSOP Type II Package
f
DQ
DQ Burst Frequency
200
266
266
MHz
鈥?Intended for 100 MHz and 133 MHz applications
鈥?Inputs and outputs are SSTL-2 compatible
鈥?V
DD
= 2.5Volt 鹵?0.2, V
DD
= 2.5Volt 鹵 0.2
鈥?Single Pulsed
RAS
interface
鈥?SDRAMs have 4 internal banks for concurrent operation
鈥?Module has one physical bank
鈥?Differential clock inputs
Description
NT128D64S88A0G is an unbuffered 184-Pin Double Data Rate (DDR) Synchronous DRAM Dual In-Line Memory Module (DIMM),
organized as a one-bank high-speed memory array. The 16Mx64 module is a single-bank DIMM that uses eight 16Mx8 DDR
SDRAMs in 400 mil TSOP packages. The DIMM achieves high-speed data transfer rates of up to 266MHz. The DIMM is intended for use
in applications operating from 100 MHz to 133 MHz clock speeds with data rates of 200 to 266 MHz. Clock enable CKE0 controls all
devices on the DIMM.
Prior to any access operation, the device
CAS
latency and burst type/ length/operation type must be programmed into the DIMM by
address inputs A0-A11 and I/O inputs BA0 and BA1 using the mode register set cycle.
These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common
design files minimizes electrical variation between suppliers.
The DIMM uses serial presence detects implemented via a serial EEPROM using the two-pin IIC protocol. The first 128 bytes of serial PD
data are programmed and locked during module assembly. The last 128 bytes are available to the customer.
All NANYA 184 DDR SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25鈥?long space-saving footprint.
Ordering Information
Part Number
NT128D64S88A0G-7K
Speed
143MHz (7ns @ CL = 2.5 )
133MHz (7.5ns @ CL= 2 )
NT128D64S88A0G 鈥?5B
133MHz (7.5ns @ CL= 2.5 )
100MHz (10ns @ CL = 2 )
NT128D64S88A0G 鈥?B
125MHz (8ns @ CL = 2.5 )
100MHz (10ns @ CL = 2 )
PC1600
PC2100
16Mx64
Gold
2.5V
PC2100
Organization
Leads
Power
REV1.0
/
June 2001
1
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
漏 NANYA TECHNOLOGY CORP.

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