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NSBC114EPDXV6T5 Datasheet

  • NSBC114EPDXV6T5

  • Dual Bias Resistor Transistors

  • 14頁

  • ONSEMI

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NSBC114EPDXV6T1,
NSBC114EPDXV6T5
Preferred Devices
Dual Bias Resistor
Transistors
NPN and PNP Silicon Surface Mount
Transistors with Monolithic Bias
Resistor Network
The BRT (Bias Resistor Transistor) contains a single transistor with
a monolithic bias network consisting of two resistors; a series base
resistor and a base鈭抏mitter resistor. These digital transistors are
designed to replace a single device and its external resistor bias
network. The BRT eliminates these individual components by
integrating them into a single device. In the NSBC114EPDXV6T1
series, two complementary BRT devices are housed in the SOT鈭?63
package which is ideal for low power surface mount applications
where board space is at a premium.
http://onsemi.com
(3)
R
1
Q
1
Q
2
R
2
(4)
R
1
(5)
(6)
(2)
R
2
(1)
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
6
54
23
Simplifies Circuit Design
Reduces Board Space
Reduces Component Count
Available in 8 mm, 7 inch Tape and Reel
Lead Free Solder Plating
1
SOT鈭?63
CASE 463A
PLASTIC
MAXIMUM RATINGS
(T
A
= 25擄C unless otherwise noted, common for Q
1
and Q
2
, 鈭?minus sign for Q
1
(PNP) omitted)
Rating
Collector-Base Voltage
Collector-Emitter Voltage
Collector Current
Symbol
V
CBO
V
CEO
I
C
Value
50
50
100
Unit
Vdc
Vdc
mAdc
MARKING DIAGRAM
xx D
THERMAL CHARACTERISTICS
Characteristic
(One Junction Heated)
Total Device Dissipation
Derate above 25擄C
Thermal Resistance Junction-to-Ambient
Characteristic
(Both Junctions Heated)
Total Device Dissipation
Derate above 25擄C
Thermal Resistance Junction-to-Ambient
Junction and Storage Temperature
1. FR鈭? @ Minimum Pad
R
qJA
T
J
, T
stg
T
A
= 25擄C
R
qJA
T
A
= 25擄C
Symbol
P
D
Max
357
(Note 1)
2.9
(Note 1)
350
(Note 1)
Max
500
(Note 1)
4.0
(Note 1)
250
(Note 1)
鈭?5 to
+150
Unit
mW
mW/擄C
擄C/W
xx = Specific Device Code
(see table on page 2)
D = Date Code
ORDERING INFORMATION
Device
Package
Shipping
4 mm pitch
4000/Tape & Reel
2 mm pitch
8000/Tape & Reel
NSBC114EPDXV6T1 SOT鈭?63
NSBC114EPDXV6T5 SOT鈭?63
Unit
mW
Symbol
P
D
DEVICE MARKING INFORMATION
mW/擄C
擄C/W
擄C
Preferred
devices are recommended choices for future use
and best overall value.
See specific marking information in the device marking table
on page 2 of this data sheet.
漏
Semiconductor Components Industries, LLC, 2004
1
January, 2004 鈭?Rev. 3
Publication Order Number:
NSBC114EPDXV6/D

NSBC114EPDXV6T5 產(chǎn)品屬性

  • ON Semiconductor

  • Transistors Switching (Resistor Biased)

  • Dual

  • PNP

  • 10 KOhms

  • 1

  • SMD/SMT

  • SOT-563-6

  • 50 V

  • 0.1 A

  • 100 mA

  • 357 mW

  • + 150 C

  • Reel

  • - 55 C

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