鈥?/div>
Filtering Circuitry
V
CC
Input Pin on First Stage to Set Microphone DC Bias
IEC 61000鈭?鈭? Grade
鹵15
kV Contact ESD Protection on the Inputs,
V
CC
, and Between Power and Analog Grounds
IEC 61000鈭?鈭? Level 1 ESD protection on All Other Pin鈭抰o鈭扨in
Combinations
These are Pb鈭扚ree Devices*
9 Bump Flip鈭扖hip
CASE 499AE
A1
6 Bump Flip鈭扖hip
CASE 499AF
A
L
Y
W
A1
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
V
CC
NMF3000FCT1G
NMF3010FCT1G
Microphone
Incoming
Audio
Signals
C
1st
Stage
C
2nd
Stage
Audio
Amplifier
Figure 1. System Diagram
*For additional information on our Pb鈭扚ree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
漏
Semiconductor Components Industries, LLC, 2004
1
March, 2004 鈭?Rev. 1
Publication Order Number:
NMF3000/D
脠脠
脠脠
脟
脟
NMF
3000
ALYW
NIO
ALYW