NLAS4053
Analog Multiplexer/
Demultiplexer
Triple 2:1 Analog Switch鈥揗ultiplexer
Improved Process, Sub鈥揗icron Silicon
Gate CMOS
The NLAS4053 is an improved version of the MC14053 and
MC74HC4053 fabricated in sub鈥搈icron Silicon Gate CMOS
technology for lower R
DS(on)
resistance and improved linearity with
low current. This device may be operated either with a single supply or
dual supply up to
鹵3
V to pass a 6 V
PP
signal without coupling
capacitors.
When operating in single supply mode, it is only necessary to tie
V
EE
, pin 7 to ground. For dual supply operation, V
EE
is tied to a
negative voltage, not to exceed maximum ratings. Pin for pin
compatible with all industry standard versions of 鈥?053.鈥?/div>
http://onsemi.com
MARKING DIAGRAMS
16
9
SO鈥?6
D SUFFIX
CASE 751B
NLAS4053
AWLYWW
1
8
16
9
鈥?/div>
Improved R
DS(on)
Specifications
鈥?/div>
Pin for Pin Replacement for MAX4053 and MAX4053A
鈥?One Half the Resistance Operating at 5.0 Volts
鈥?/div>
Single or Dual Supply Operation
鈥?Single 3鈥? Volt Operation, or Dual
鹵3
Volt Operation
鈥?With V
CC
of 3.0 to 3.3 V, Device Can Interface with 1.8 V Logic,
鈥?/div>
No Translators Needed
鈥?Address and Inhibit Pins are Over鈥揤oltage Tolerant and May Be
鈥?/div>
Driven Up +6 V Regardless of V
CC
鈥?/div>
Address and Control Pins are Standard TTL Compatible
鈥?Greatly Improved Noise Margin Over MAX4053 and MAX4053A
鈥?/div>
Improved Linearity Over Standard HC4053 Devices
TSSOP鈥?6
DT SUFFIX
CASE 948F
NLAS
4053
ALYW
1
8
16
9
QSOP鈥?6
QS SUFFIX
CASE 492
A
L, WL
Y, YY
W, WW
NLAS
4053
ALYW
1
8
鈥?/div>
Popular SOIC, and Space Saving TSSOP, and QSOP 16 Pin
Packages
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
NLAS4053D
NLAS4053DR2
NLAS4053DT
NLAS4053DTR2
NLAS4053QS
NLAS4053QSR
Package
SO鈥?6
SO鈥?6
TSSOP鈥?6
TSSOP鈥?6
QSOP鈥?6
QSOP鈥?6
Shipping
48 Units/Rail
2500 Units/Reel
96 Units/Rail
2500 Units/Reel
48 Units/Rail
2000 Units/Reel
漏
Semiconductor Components Industries, LLC, 2002
1
June, 2002 鈥?Rev. 0
Publication Order Number:
NLAS4053/D
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