鈥?/div>
Extremely High Speed: t
PD
2.0 ns (typical) at V
CC
= 5 V
Designed for 1.65 V to 5.5 V V
CC
Operation
Over Voltage Tolerant Inputs and Outputs
LVTTL Compatible 鈥?Interface Capability With 5 V TTL Logic with
V
CC
= 3 V
LVCMOS Compatible
24 mA Balanced Output Sink and Source Capability
Near Zero Static Supply Current Substantially Reduces System
Power Requirements
Chip Complexity: FET = 72
http://onsemi.com
MARKING
DIAGRAM
8
8
1
US8
US SUFFIX
CASE 493鈥?1
L5
1
D
D = Date Code
IN A1
1
8
V
CC
OUT Y3
2
7
OUT Y1
PIN ASSIGNMENT
1
IN A2
3
6
IN A3
2
3
GND
4
5
OUT Y2
4
5
6
IN A1
OUT Y3
IN A2
GND
OUT Y2
IN A3
OUT Y1
V
CC
Figure 1. Pinout
(Top View)
7
8
IN A1
IN A2
IN A3
OUT Y1
OUT Y2
OUT Y3
FUNCTION TABLE
A Input
L
H
Y Output
H
L
Figure 2. Logic Symbol
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
漏
Semiconductor Components Industries, LLC, 2002
1
August, 2002 鈥?Rev. 2
Publication Order Number:
NL37WZ04/D