鈫?/div>
D
X
X
X
h
l
X
Outputs
Q
H
L
H
H
L
NC
Q
L
H
H
L
H
NC
Figure 1. Logic Diagram
Operating Mode
Asynchronous Set
Asynchronous Clear
Undetermined
Load and Read Register
Hold
US8
CASE 493
US SUFFIX
MARKING DIAGRAM
= High Voltage Level
= High Voltage Level One Setup Time Prior to the Low鈥搕o鈥揌igh Clock Transition
= Low Voltage Level
= Low Voltage Level One Setup Time Prior to the Low鈥搕o鈥揌igh Clock Transition
= No Change
= High or Low Voltage Level and Transitions are Acceptable
= Low鈥搕o鈥揌igh Transition
= Not a Low鈥搕o鈥揌igh Transition
MH
D
MH = Specific Device Code
D
= Date Code
For I
CC
reasons, DO NOT FLOAT Inputs
PINOUT
CP
D
Q
GND
1
2
3
4
8
7
6
5
V
CC
PR
CLR
Q
ORDERING INFORMATION
Device
NL17SZ74US
Package
US8
Shipping
3000/Tape & Reel
漏
Semiconductor Components Industries, LLC, 2002
1
May, 2002 鈥?Rev. 2
Publication Order Number:
NL17SZ74/D