鈥?/div>
Tiny SOT鈭?53 and SOT鈭?53 Packages
Source/Sink 24 mA at 3.0 Volts
Over鈭扸
oltage Tolerant Inputs and Outputs
Chip Complexity: FETs = 20
Designed for 1.65 V to 5.5 V V
CC
Operation
Pb鈭扚ree Packages are Available
http://onsemi.com
MARKING
DIAGRAMS
5
1
SOT鈭?53/SC70鈭?/SC鈭?8A
DF SUFFIX
CASE 419A
d = Date Code
5
5
LR D
1
1
5
LR
d
NC
1
5
V
CC
1
SOT鈭?53
XV5 SUFFIX
CASE 463B
A
2
LR = Device Marking
D
= One Digit Date Code
4
Y
GND
3
PIN ASSIGNMENT
Pin
Function
NC
IN A
GND
OUT Y
V
CC
Figure 1. Pinout
(Top View)
1
2
3
A
1
Y
4
5
Figure 2. Logic Symbol
FUNCTION TABLE
A Input
L
H
Y Output
L
H
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
漏
Semiconductor Components Industries, LLC, 2005
1
January, 2005 鈭?Rev. 5
Publication Order Number:
NL17SZ16/D