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NL17SZ126DF Datasheet

  • NL17SZ126DF

  • LOGIC GATE|BUFFER|CMOS|TSSOP|6PIN|PLASTIC

  • 8頁(yè)

  • ETC

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NL17SZ126
Non-inverting 3-State
Buffer
The NL17SZ126 is a high performance dual noninverting buffer
operating from a 2.3 V to 5.5 V supply.
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Extremely High Speed: t
PD
2.6 ns (typical) at V
CC
= 5 V
Designed for 2.3 V to 5.5 V V
CC
Operation
Over Voltage Tolerant Inputs and Outputs
LVTTL Compatible 鈥?Interface Capability With 5 V TTL Logic with
V
CC
= 3 V
LVCMOS Compatible
24 mA Balanced Output Sink and Source Capability
Near Zero Static Supply Current Substantially Reduces System
Power Requirements
3鈥揝tate OE Input is Active HIGH
Replacement for NC7SZ126
Chip Complexity = 36 Feet
Figure 1.
http://onsemi.com
MARKING
DIAGRAMS
5
5
1
SC70鈥?/SC鈥?8A/SOT鈥?53
DF SUFFIX
CASE 419A
d = Date Code
1
M2
d
PIN ASSIGNMENT
1
2
3
OE
IN A
GND
OUT Y
V
CC
OE
1
5
V
CC
4
5
IN A
2
OE Input
FUNCTION TABLE
A Input
L
H
X
Y Output
L
H
Z
GND
3
4
OUT Y
H
H
L
X = Don鈥檛 Care
Figure 1. Pinout
(Top View)
ORDERING INFORMATION
OE
IN A
OUT Y
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
Figure 2. Logic Symbol
漏
Semiconductor Components Industries, LLC, 2002
1
April, 2002 鈥?Rev. 1
Publication Order Number:
NL17SZ126/D

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