鈭?/div>
Interface Capability with 5.0 V TTL Logic with
V
CC
= 2.7 V to 3.6 V
LVCMOS Compatible
24 mA Output Sink Capability, Pullup may be between 0 and 7.0 V
Near Zero Static Supply Current Substantially Reduces System
Power Requirements
Chip Complexity: FET = 20
Pb鈭扚ree Packages are Available
SC鈭?8A / SOT鈭?53 / SC鈭?0
DF SUFFIX
CASE 419A
VX M
G
G
SOT鈭?53
XV5 SUFFIX
CASE 463B
L7 D
G
G
NC
1
OVT
5
V
CC
M
= Date Code
A
= Assembly Location
Y
= Year
W
= Work Week
G
= Pb鈭扚ree Package
(Note: Microdot may be in either location)
IN A
2
Pin
PIN ASSIGNMENT
Function
NC
IN A
GND
OUT Y
V
CC
1
2
3
GND
3
4
OUT Y
Figure 1. Pinout
4
5
IN A
1
OUT Y
L
H
FUNCTION TABLE
A Input
Y Output
L
Z
Figure 2. Logic Symbol
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
漏
Semiconductor Components Industries, LLC, 2005
August, 2005
鈭?/div>
Rev. 5
1
Publication Order Number:
NL17SZ07/D
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