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NID9N05CL Datasheet

  • NID9N05CL

  • Power MOSFET

  • 8頁

  • ONSEMI

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NID9N05CL
Power MOSFET
9.0 A, 52 V, N鈭扖hannel, Logic Level,
Clamped MOSFET w/ ESD Protection
in a DPAK Package
http://onsemi.com
Benefits
鈥?/div>
High Energy Capability for Inductive Loads
鈥?/div>
Low Switching Noise Generation
Features
V
DSS
(Clamped)
52 V
R
DS(ON)
TYP
90 m鈩?/div>
I
D
MAX
(Limited)
9.0 A
Drain
(Pins 2, 4)
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Diode Clamp Between Gate and Source
ESD Protection 鈭?HBM 5000 V
Active Over鈭扸oltage Gate to Drain Clamp
Scalable to Lower or Higher R
DS(on)
Internal Series Gate Resistance
Applications
Gate
(Pin 1)
R
G
Overvoltage
Protection
M
PWR
鈥?/div>
Automotive and Industrial Markets:
Solenoid Drivers, Lamp Drivers, Small Motor Drivers
MAXIMUM RATINGS
(T
J
= 25擄C unless otherwise noted)
Rating
Drain鈭抰o鈭扴ource Voltage Internally Clamped
Gate鈭抰o鈭扴ource Voltage 鈭?Continuous
Drain Current 鈭?Continuous @ T
A
= 25擄C
Drain Current
鈭?Single Pulse (t
p
= 10
ms)
Total Power Dissipation @ T
A
= 25擄C
Operating and Storage Temperature Range
Single Pulse Drain鈭抰o鈭扴ource Avalanche
Energy 鈭?Starting T
J
= 125擄C
(V
DD
= 50 V, I
D(pk)
= 1.5 A, V
GS
= 10 V,
R
G
= 25
W)
Thermal Resistance 鈭?Junction鈭抰o鈭扖ase
鈭?Junction鈭抰o鈭扐mbient (Note 1)
鈭?Junction鈭抰o鈭扐mbient (Note 2)
Maximum Lead Temperature for Soldering
Purposes, 1/8鈥?from Case for 10 s
Symbol
V
DSS
V
GS
I
D
I
DM
P
D
T
J
, T
stg
E
AS
Value
52鈭?9
鹵15
9.0
35
28.8
鈭?5 to
175
160
Unit
V
V
A
W
擄C
mJ
ESD Protection
Source
(Pin 3)
MARKING
DIAGRAM
1
DPAK
CASE 369C
STYLE 2
D9N05CL
A
Y
WW
2
3
1
2
3
4
= Gate
= Drain
= Source
= Drain
AYWW
D9N05CL
4
R
qJC
R
qJA
R
qJA
T
L
5.2
72
100
260
擄C/W
= Device Code
= Assembly Location
= Year
= Work Week
ORDERING INFORMATION
擄C
Device
NID9N05CLT4
NID9N05CL
Package
DPAK
DPAK
Shipping
鈥?/div>
2500/Tape & Reel
75 Units/Rail
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. When surface mounted to an FR4 board using 1鈥?pad size, (Cu area 1.127 in
2
)
2. When surface mounted to an FR4 board using minimum recommended pad
size, (Cu area 0.412 in
2
)
鈥燜or information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
漏
Semiconductor Components Industries, LLC, 2004
1
July, 2004 鈭?Rev. 5
Publication Order Number:
NID9N05CL/D

NID9N05CL 產(chǎn)品屬性

  • 75

  • 集成電路 (IC)

  • PMIC - MOSFET，電橋驅(qū)動器 - 內(nèi)部開關(guān)

  • -

  • 低端

  • 非反相

  • 1

  • 153 毫歐

  • -

  • 9A

  • -

  • -55°C ~ 175°C

  • 表面貼裝

  • TO-252-3，DPak（2 引線+接片），SC-63

  • DPAK-3

  • 管件

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