80960KB
80960KB
EMBEDDED 32-BIT MICROPROCESSOR
WITH INTEGRATED FLOATING-POINT UNIT
s
High-Performance Embedded
s
Built-in Interrupt Controller
Architecture
鈥?25 MIPS Burst Execution at 25 MHz
鈥?9.4 MIPS* Sustained Execution at
25 MHz
s
512-Byte On-Chip Instruction Cache
鈥?Direct Mapped
鈥?Parallel Load/Decode for Uncached
Instructions
s
Multiple Register Sets
鈥?Sixteen Global 32-Bit Registers
鈥?Sixteen Local 32-Bit Registers
鈥?Four Local Register Sets Stored
On-Chip
鈥?Register Scoreboarding
s
4 Gigabyte, Linear Address Space
s
Pin Compatible with 80960KA
鈥?31 Priority Levels, 256 Vectors
鈥?3.4 碌s Latency @ 25 MHz
s
Easy to Use, High Bandwidth 32-Bit Bus
鈥?66.7 Mbytes/s Burst
鈥?Up to 16 Bytes Transferred per Burst
s
132-Lead Packages:
鈥?Pin Grid Array (PGA)
鈥?Plastic Quad Flat-Pack (PQFP)
s
On-Chip Floating Point Unit
鈥?Supports IEEE 754 Floating Point
Standard
鈥?Four 80-Bit Registers
鈥?13.6 Million Whetstones/s (Single
Precision) at 25 MHz
FOUR
80-BIT FP
REGISTERS
80-BIT
FPU
SIXTEEN
32-BIT GLOBAL
REGISTERS
64- BY 32-BIT
LOCAL
REGISTER
CACHE
32-BIT
INSTRUCTION
EXECUTION
UNIT
32-BIT
BUS CONTROL
LOGIC
INSTRUCTION
FETCH UNIT
512-BYTE
INSTRUCTION
CACHE
INSTRUCTION
DECODER
MICRO-
INSTRUCTION
SEQUENCER
MICRO-
INSTRUCTION
ROM
32-BIT
BURST
BUS
Figure 1. The 80960KB Processor鈥檚 Highly Parallel Architecture
漏 INTEL CORPORATION, 1997
June, 1997
Order Number:
270565.007