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NE564D Datasheet

  • NE564D

  • Phase-locked loop

  • 9頁

  • PHILIPS

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Philips Semiconductors
Product specification
Phase-locked loop
NE/SE564
DESCRIPTION
The NE/SE564 is a versatile, high guaranteed frequency
phase-locked loop designed for operation up to 50MHz. As shown
in the Block Diagram, the NE/SE564 consists of a VCO, limiter,
phase comparator, and post detection processor.
PIN CONFIGURATIONS
D, N Packages
V+
LOOP GAIN CONTROL
INPUT TO PHASE COMP
FROM VCO
LOOP FILTER
LOOP FILTER
FM/RF INPUT
BIAS FILTER
GND
1
2
3
4
5
6
7
8
16 TTL OUTPUT
15 HYSTERESIS SET
14 ANALOG OUT
13 FREQ. SET CAP
12 FREQ. SET CAP
11
VCO OUT 2
FEATURES
鈥?/div>
Operation with single 5V supply
鈥?/div>
TTL-compatible inputs and outputs
鈥?/div>
Guaranteed operation to 50MHz
鈥?/div>
External loop gain control
鈥?/div>
Reduced carrier feedthrough
鈥?/div>
No elaborate filtering needed in FSK applications
鈥?/div>
Can be used as a modulator
鈥?/div>
Variable loop gain (externally controlled)
APPLICATIONS
10 V+
9
VCO OUT TTL
TOP VIEW
SR01025
鈥?/div>
High speed modems
鈥?/div>
FSK receivers and transmitters
鈥?/div>
Frequency Synthesizers
ORDERING INFORMATION
DESCRIPTION
16-Pin Plastic Small Outline (SO) Package
16-Pin Plastic Dual In-Line Package (DIP)
16-Pin Plastic Dual In-Line Package (DIP)
Figure 1. Pin Configuration
鈥?/div>
Signal generators
鈥?/div>
Various satcom/TV systems
鈥?/div>
pin configuration
TEMPERATURE RANGE
0 to +70擄C
0 to +70擄C
-55 to +125擄C
ORDER CODE
NE564D
NE564N
SE564N
DWG #
SOT109-1
SOT38-4
SOT38-4
BLOCK DIAGRAM
V
+
4
5
1
14
LIMITER
6
PHASE
COMPARATOR
2
DC
7
3
11
9
VCO
10
12
13
8
AMPLIFIER
RETRIEVER
SCHMITT
TRIGGER
16
POST DETECTION
PROCESSOR
15
SR01026
Figure 2. Block Diagram
1994 Aug 31
1
853-0908 13720

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