NDS355 Datasheet

IC型號(hào)：
NDS355
PDF描述：
N-Channel Logic Level Enhancement Mode Field Effect Transist...
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77.44KB
PDF頁(yè)數(shù)：
6頁(yè)
芯片廠(chǎng)家：
FAIRCHILD

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March 1996

NDS355N

N-Channel Logic Level Enhancement Mode Field Effect Transistor

General Description

These N-Channel logic level enhancement mode power field

effect transistors are produced using Fairchild's proprietary,

high cell density, DMOS technology. This very high density

process is especially tailored to minimize on-state resistance.

These devices are particularly suited for low voltage

applications in notebook computers, portable phones, PCMICA

cards, and other battery powered circuits where fast switching,

and low in-line power loss are needed in a very small outline

surface mount package.

Features

1.6A, 30V. R

DS(ON)

= 0.125

鈩?/div>

@ V

= 4.5V.

Proprietary package design using copper lead frame for

superior thermal and electrical capabilities.

High density cell design for extremely low R

DS(ON)

Exceptional on-resistance and maximum DC current

capability.

Compact industry standard SOT-23 surface mount

package.

_______________________________________________________________________________

Absolute Maximum Ratings

Symbol

DSS

GSS

STG

Parameter

Drain-Source Voltage

= 25擄C unless otherwise noted

NDS355N

(Note 1a)

Units

Gate-Source Voltage - Continuous

Drain Current - Continuous

- Pulsed

Maximum Power Dissipation

(Note 1b)

(Note 1a)

鹵 1.6

鹵 10

0.5

0.46

-55 to 150

Operating and Storage Temperature Range

擄C

THERMAL CHARACTERISTICS

胃

Thermal Resistance, Junction-to-Ambient

Thermal Resistance, Junction-to -Case

(Note 1a)

(Note 1)

250

擄C/W

漏 1997 Fairchild Semiconductor Corporation

NDS355N Rev. D1

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