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NBSG53AMNR2 Datasheet

  • NBSG53AMNR2

  • 2.5V/3.3V SiGe Selectable Differential Clock and Data D Flip...

  • 18頁

  • ONSEMI

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NBSG53A
2.5V/3.3V SiGe Selectable
Differential Clock and Data
D Flip鈭扚lop/Clock Divider
with Reset and OLS*
The NBSG53A is a multi鈭抐unction differential D flip鈭抐lop (DFF) or
fixed divide by two (DIV/2) clock generator. This is a part of the
GigaComm鈩?family of high performance Silicon Germanium
products. A strappable control pin is provided to select between the
two functions. The device is housed in a low profile 4x4 mm 16鈭抪in
Flip鈭扖hip BGA (FCBGA) or a 3x3 mm 16 pin QFN package.
The NBSG53A is a device with data, clock, OLS, reset, and select
inputs. Differential inputs incorporate internal 50
W
termination
resistors and accept NECL (Negative ECL), PECL (Positive ECL),
LVCMOS/LVTTL, CML, or LVDS. The OLS input is used to
program the peak鈭抰o鈭抪eak output amplitude between 0 and 800 mV
in five discrete steps. The RESET and SELECT inputs are
single鈭抏nded and can be driven with either LVECL or
LVCMOS/LVTTL input levels.
Data is transferred to the outputs on the positive edge of the clock.
The differential clock inputs of the NBSG53A allow the device to also
be used as a negative edge triggered device.
http://onsemi.com
MARKING
DIAGRAM**
SG
53A
LYW
FCBGA鈭?6
BA SUFFIX
CASE 489
QFN鈭?6
MN SUFFIX
CASE 485G
SG53A
ALYW
鈥?/div>
Maximum Input Clock Frequency (DFF) > 8 GHz Typical
(See Figures 4, 6, 8, 10, and 11)
鈥?/div>
Maximum Input Clock Frequency (DIV/2) > 10 GHz Typical
(See Figures 5, 7, 9, 10, and 11)
鈥?/div>
210 ps Typical Propagation Delay (OLS = FLOAT)
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
**For further details, refer to Application
Note AND8002/D
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
45 ps Typical Rise and Fall Times (OLS = FLOAT)
DIV/2 Mode (Active with Select Low)
DFF Mode (Active with Select High)
Board
NBSG53ABAEVB
Description
NBSG53ABA Evaluation Board
Selectable Swing PECL Output with Operating Range: V
CC
= 2.375 V
to 3.465 V with V
EE
= 0 V
鈥?/div>
Selectable Swing NECL Output with NECL Inputs with
Operating Range: V
CC
= 0 V with V
EE
= 鈭?.375 V to 鈭?.465 V
鈥?/div>
Selectable Output Level (0 V, 200 mV, 400 mV, 600 mV, or 800 mV
Peak鈭抰o鈭扨eak Output)
鈥?/div>
50
W
Internal Input Termination Resistors on all Differential Inputs
*Output Level Select
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 16 of this data sheet.
漏
Semiconductor Components Industries, LLC, 2004
1
March, 2004 鈭?Rev. 5
Publication Order Number:
NBSG53A/D

NBSG53AMNR2 產(chǎn)品屬性

  • 3,000

  • 集成電路 (IC)

  • 邏輯 - 觸發(fā)器

  • -

  • 復(fù)位

  • D 型總線

  • 差分

  • 1

  • 2

  • 8GHz

  • -

  • 正，負(fù)

  • -

  • 2.375 V ~ 3.465 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 16-VFQFN 裸露焊盤

  • 帶卷 (TR)

  • NBSG53AMNR2OSTR

NBSG53AMNR2相關(guān)型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    2.5V/3.3VSiGe 1:2 Differential Clock Driver with RSECL* Out...
    ONSEMI
  • 英文版
    2.5V/3.3VSiGe 1:2 Differential Clock Driver with RSECL* Out...
    ONSEMI [ON...
  • 英文版
    2.5V/3.3V SiGe Differential 1:4 Clock/Data Driver with RSECL...
    ONSEMI
  • 英文版
    2.5V/3.3V SiGe Differential 1:4 Clock/Data Driver with RSECL...
    ONSEMI [ON...
  • 英文版
    2.5V/3.3V SiGe Differential Receiver/Driver with RSECLOutput...
    ONSEMI
  • 英文版
    2.5V/3.3V SiGe Differential Receiver/Driver with RSECLOutput...
    ONSEMI [ON...
  • 英文版
    2.5V/3.3VSiGe Differential 1:10 Clock/Data Driver with RSEC...
  • 英文版
    2.5V/3.3VMultilevel Input to CML Clock/Data Receiver/Drive...
    ONSEMI
  • 英文版
    2.5V/3.3VMultilevel Input to CML Clock/Data Receiver/Drive...
    ONSEMI [ON...
  • 英文版
    2.5V/3.3V SiGe Selectable Differential Clock and Data D Flip...
    ONSEMI
  • 英文版
    2.5V/3.3V SiGe Selectable Differential Clock and Data D Flip...
    ONSEMI [ON...
  • 英文版
    2.5V/3.3VSiGe Differential 2 X 2 Crosspoint Switch with Out...
    ONSEMI
  • 英文版
    2.5V/3.3VSiGe Differential 2 X 2 Crosspoint Switch with Out...
    ONSEMI [ON...
  • 英文版
    Evaluation Board Manual
    ONSEMI
  • 英文版
    Evaluation Board Manual
    ONSEMI [ON...
  • 英文版
    2.5V/3.3VSiGe Differential Smart Gate with Output Level Sel...
    ONSEMI [ON...
  • 英文版
    2.5V/3.3V SiGe 1:2 Differential Clock Driver with RSECL Outp...
    ONSEMI
  • 英文版
    2.5V/3.3VSiGe 1:2 Differential Clock Driver with RSECL* Out...
    ONSEMI
  • 英文版
    2.5V/3.3VSiGe 1:2 Differential Clock Driver with RSECL* Out...
    ONSEMI [ON...
  • 英文版
    2.5V/3.3V SiGe 1:2 Differential Clock Driver with RSECL Outp...
    ON Semiconductor

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