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NB7N017MMN Datasheet

  • NB7N017MMN

  • 3.3V SiGe 8-Bit Dual Modulus Programmable Divider/Prescaler ...

  • 20頁

  • ONSEMI

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NB7N017M
3.3V SiGe 8鈭払it Dual
Modulus Programmable
Divider/Prescaler with CML
Outputs
The NB7N017M is a high speed 8鈥揵it dual modulus
programmable divider/prescaler with 16 mA CML outputs capable
of switching at input frequencies greater than 3.5 GHz. The CML
output structure contains internal 50
W
source termination resistor to
V
CC
. The device generates 400 mV output amplitude with 50
W
receiver resistor to V
CC
. This I/O structure enables easy
implementation of the NB7N017M in 50
W
systems.
The differential inputs contain 50
W
termination resistors to VT
pads and all differential inputs accept RSECL, ECL, LVDS,
LVCMOS, LVTTL, and CML.
Internally, the NB7N017M uses a > 3.5 GHz 8鈥揵it programmable
down counter. A select pin, SEL, is used to select between two
words, Pa[0:7] and Pb[0:7], that are stored in REGa and REGb
respectively. Two parallel load pins, PLa and PLb, are used to load
the level triggered programming registers, REGa and REGb,
respectively. A differential clock enable, CE, pin is available.
The NB7N017M offers a differential output, TC. Terminal count
output, TC, goes high for one clock cycle when the counter has
reached the all zeros state. To reduce output phase noise, TC is
retimed with the rising edge triggered latches.
鈥?/div>
Maximum Input Clock Frequency > 3.5 GHz Typical
鈥?/div>
Differential CLK Clock Input
鈥?/div>
Differential CE Clock Enable Input
鈥?/div>
Differential SEL Word Select Input
鈥?/div>
50
W
Internal Input and Output Termination Resistors
鈥?/div>
Differential TC Terminal Count Output
鈥?/div>
All Outputs 16 mA CML with 50
W
Internal Source Termination
to V
CC
鈥?/div>
All Single鈥揈nded Control Pins CMOS and PECL/NECL
Compatible
鈥?/div>
Counter Programmed Using One of Two Single鈭扙nded Words,
Pa[0:7] and Pb[0:7], Stored in REGa and REGb
鈥?/div>
REGa and REGb Implemented with Level Triggered Latch
鈥?/div>
Compatible with Existing 3.3 V LVEP, EP, and SG Devices
鈥?/div>
Ability to Program the Divider without Disturbing Current Settings
鈥?/div>
Positive CML Output Operating Range: V
CC
= 3.0 V to 3.465 V
with V
EE
= 0 V
鈥?/div>
Negative CML Output Operating Range: V
CC
= 0 V
with V
EE
= 鈥?.0 V to 鈥?.465 V
鈥?/div>
V
BB
Reference Voltage Output
鈥?/div>
CML Output Level: 400 mV Peak鈭扨eak Output with 50
W
Receiver
Resistor to V
CC
鈥?/div>
Pb鈭扚ree Packages are Available*
http://onsemi.com
1
52
QFN鈭?2
MN SUFFIX
CASE 485M
MARKING DIAGRAM*
52
1
NB7N
017M
AWLYYWW
NB7N017M
A
WL
YY
WW
= Device Code
= Assembly Site
= Wafer Lot
= Year
= Work Week
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 18 of this data sheet.
*For additional information on our Pb鈭扚ree strategy
and soldering details, please download the ON Semi-
conductor Soldering and Mounting Techniques Ref-
erence Manual, SOLDERRM/D.
錚?/div>
Semiconductor Components Industries, LLC, 2004
November, 2004
鈭?/div>
Rev. 0
1
Publication Order Number:
NB7N017M/D

NB7N017MMN 產品屬性

  • 260

  • 集成電路 (IC)

  • 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器

  • -

  • 時鐘除法器

  • 無

  • CML，ECL，LVCMOS，LVDS，LVTTL

  • CML

  • 1

  • 1:1

  • 是/是

  • 3.5GHz

  • 是/無

  • ±3 V ~ 3.465 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 52-VFQFN 裸露焊盤

  • 52-QFN（8x8）

  • 管件

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