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NB7L86M Datasheet

  • NB7L86M

  • 2.5V/3.3V 12 Gb/s Differential Clock/Data SmartGate with CML...

  • 12頁

  • ONSEMI

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NB7L86M
2.5V/3.3V 12 Gb/s Differential
Clock/Data SmartGate with
CML Output and Internal
Termination
The NB7L86M is a multi鈭抐unction differential Logic Gate, which
can be configured as an AND/NAND, OR/NOR, XOR/XNOR, or 2:1
MUX. This device is part of the GigaComm family of high
performance Silicon Germanium products. The NB7L86M is an
ultra鈭抣ow jitter multi鈭抣ogic gate with a maximum data rate of 12 Gb/s
and input clock frequency of 8 GHz suitable for Data Communication
Systems, Telecom Systems, Fiber Channel, and GigE applications.
Differential inputs incorporate internal 50
W
termination resistors
and accept LVNECL (Negative ECL), LVPECL (Positive ECL),
LVCMOS, LVTTL, CML, or LVDS. The differential 16 mA CML
output provides matching internal 50
W
termination, and 400 mV
output swing when externally terminated 50
W
to V
CC
.
The device is housed in a low profile 3x3 mm 16鈭抪in QFN package.
Application notes, models, and support documentation are available
on www.onsemi.com.
Features
http://onsemi.com
MARKING
DIAGRAM*
16
1
QFN鈭?6
MN SUFFIX
CASE 485G
NB7L
86M
ALYWG
G
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb鈭扚ree Package
Maximum Input Clock Frequency up to 8 GHz
Maximum Input Data Rate up to 12 Gb/s Typical
< 0.5 ps of RMS Clock Jitter
< 10 ps of Data Dependent Jitter
*For additional marking information, refer to
Application Note AND8002/D.
30 ps Typical Rise and Fall Times
90 ps Typical Propagation Delay
2 ps Typical Within Device Skew
Operating Range: V
CC
= 2.375 V to 3.465 V with V
EE
= 0 V
CML Output Level (400 mV Peak鈭抰o鈭扨eak Output) Differential Output
50
W
Internal Input and Output Termination Resistors
Functionally Compatible with Existing 2.5 V/3.3 V LVEL, LVEP, EP
and SG Devices
鈥?/div>
Pb鈭扚ree Packages are Available
VTD0
D0
D0
VTD0
50
W
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
Q
50
W
50
W
Q
VTD1
D1
D1
VTD1
50
W
50
W
SEL
50
W
VTSEL
SEL
Figure 1. Simplified Logic Diagram
Semiconductor Components Industries, LLC, 2006
January, 2006
鈭?/div>
Rev. 3
1
Publication Order Number:
NB7L86M/D

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