NB6L611
2.5V / 3.3V 1:2 Differential
LVPECL Clock / Data Fanout
Buffer
Multi鈭扡evel Inputs with Internal Termination
Description
http://onsemi.com
MARKING
DIAGRAM*
1
QFN鈭?6
MN SUFFIX
CASE 485G
16
NB6L
611
ALYWG
G
The NB6L611 is a differential 1:2 fanout buffer. The differential
inputs incorporate internal 50
W
termination resistors that are accessed
through the VTD pins and will accept LVPECL, CML, LVDS,
LVCMOS or LVTTL logic levels.
The V
REFAC
pin is an internally generated voltage supply available
to this device only. V
REFAC
is used as a reference voltage for
single鈭抏nded PECL or NECL inputs. For all single鈭抏nded input
conditions, the unused complementary differential input is connected
to V
REFAC
as a switching reference voltage. V
REFAC
may also rebias
capacitor鈭抍oupled inputs. When used, decouple V
REFAC
with a
0.01
mF
capacitor and limit current sourcing or sinking to 0.5 mA.
When not used, V
REFAC
output should be left open.
The device is housed in a small 3x3 mm 16 pin QFN package.
The NB6L611 is a member of the ECLinPS MAX鈩?family of high
performance clock products.
Features
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb鈭扚ree Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
Q0
VTD
D
D
VTD
Q0
Q1
Q1
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Maximum Input Clock Frequency > 4.0 GHz, Typical
280 ps Typical Propagation Delay
100 ps Typical Rise and Fall Times
0.5 ps maximum RMS Clock Jitter
Differential LVPECL Outputs, 780 mV Amplitude, typical
LVPECL Operating Range: V
CC
= 2.375 V to 3.63 V with V
EE
= 0 V
NECL Operating Range: V
CC
= 0 V with V
EE
=
鈭?.375
V to
鈭?.63
V
Internal Input Termination Resistors, 50
W
V
REFAC
Reference Output Voltage
Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP,
EP, and SG Devices
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鈭?0擄C
to +85擄C Ambient Operating Temperature
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These are Pb鈭扚ree Devices
Figure 1. Simplified Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
漏
Semiconductor Components Industries, LLC, 2006
December, 2006
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Rev. 0
1
Publication Order Number:
NB6L611/D
NB6L611MNR2G相關(guān)型號PDF文件下載
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型號
版本
描述
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英文版
2.5V / 3.3V MULTILEVEL INPUT TO DIFFERENTIAL LVPECL/LVNECL 1...
ONSEMI
-
英文版
2.5V / 3.3V MULTILEVEL INPUT TO DIFFERENTIAL LVPECL/LVNECL 1...
ONSEMI [ON...
-
英文版
2.5 V/3.3 V 3.0 GHz Differential 1:4 LVPECL Fanout Buffer
ONSEMI
-
英文版
2.5 V/3.3 V 3.0 GHz Differential 1:4 LVPECL Fanout Buffer
ONSEMI [ON Semi...
-
英文版
2.5V / 3.3V Multilevel Input to Differential LVPECL/LVNECL C...
ONSEMI
-
英文版
2.5V / 3.3V Multilevel Input to Differential LVPECL/LVNECL C...
ONSEMI [ON...
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英文版
2.5V / 3.3V Differential 2 X 2 Crosspoint Switch with LVPECL...
ONSEMI
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英文版
2.5V / 3.3V Differential 2 X 2 Crosspoint Switch with LVPECL...
ONSEMI [ON Semi...
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英文版
2.5V / 3.3V MULTILEVEL INPUT TO DIFFERENTIAL LVPECL/LVNECL 1...
ONSEMI
-
英文版
2.5V / 3.3V MULTILEVEL INPUT TO DIFFERENTIAL LVPECL/LVNECL 1...
ONSEMI [ON...
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英文版
2.5V / 3.3V 1:2 Differential CML Fanout Buffer
ONSEMI [ON Semi...
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英文版
2.5 V 1:2 AnyLevel TM Input to LVDS Fanout Buffer / Translat...
ONSEMI [ON Semi...
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英文版
2.5 V/3.3 V 3.0 GHz Differential 1:4 CML Fanout Buffer
ONSEMI
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英文版
2.5 V/3.3 V 3.0 GHz Differential 1:4 CML Fanout Buffer
ONSEMI [ON Semi...
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英文版
2.5 V 1:4 AnyLevel?? Differential Input to LVDS Fanout Buffe...
ONSEMI [ON Semi...
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英文版
2.5V / 3.3V Multilevel Input to Differential LVPECL/LVNECL C...
ONSEMI
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英文版
2.5V / 3.3V Multilevel Input to Differential LVPECL/LVNECL C...
ONSEMI [ON...
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英文版
2.5 V / 3.3 V Any Differential Clock IN to Differential LVPE...
ONSEMI
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英文版
2.5 V / 3.3 V Any Differential Clock IN to Differential LVPE...
ONSEMI [ON...
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英文版
2.5V / 3.3V 1:2 Differential LVPECL Clock / Data Fanout Buff...
ONSEMI
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