鈥?/div>
Maximum Clock Input Frequency, 3.0 GHz
CLOCK Inputs Compatible with LVDS/LVPECL/CML/HSTL
EN, MR, and SEL Inputs Compatible with LVTTL/LVCMOS
Rise/Fall Time 65 ps Typical
< 10 ps Typical Output鈭抰o鈭扥utput Skew
Example: 622.08 MHz Input Generates 38.88 MHz to 622.08 MHz
Outputs
Internal 50
W
Termination Provided
Random Clock Jitter < 1 ps RMS
QA
B1
Edge Aligned to QBBn Edge
Operating Range: V
CC
= 2.375 V to 3.465 V with V
EE
= 0 V
Master Reset for Synchronization of Multiple Chips
V
BBAC
Reference Output
Synchronous Output Enable/Disable
Pb鈭扚ree Packages are Available
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb鈭扚ree Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
漏
Semiconductor Components Industries, LLC, 2006
1
December, 2006 鈭?Rev. 5
Publication Order Number:
NB6L239/D