鈥?/div>
Maximum Clock Input Frequency, 3 GHz
CLK0
Maximum Input Data Rate, 3 Gb/s
CLK0
Differential LVPECL Inputs and Outputs
Low Output Skew: 50 ps Maximum Output鈭抰o鈭扥utput Skew
Synchronous Output Enable Eliminating Output Runt Pulse
Generation and Metastability
CLK1
Operating Range: Single 3.3 V or 2.5 V Supply
CLK1
V
CC
= 2.375 V to 3.465 V
LVCMOS Compatible Control Inputs
SEL0
Packaged in LQFP鈭?2
SEL1
Fully Differential Architecture
鈭?0擄C
to 85擄C Ambient Operating Temperature
OEA
These are Pb鈭扚ree Devices*
OEB
V
CC
0
Bank A
1
QA0
QA0
QA1
QA1
QA2
QA2
V
CC
0
Bank B
1
QB0
QB0
QB1
QB1
QB2
QB2
Figure 1. Functional Block Diagram
*For additional information on our Pb鈭扚ree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
漏
Semiconductor Components Industries, LLC, 2006
August, 2006
鈭?/div>
Rev. 1
1
Publication Order Number:
NB4L6254/D
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