鈥?/div>
These are Pb鈭扚ree Devices*
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb鈭扚ree Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
VTD
D
D
VTD
VTCLK
CLK
CLK
VTCLK
Clock
Reset
Q
Data
Q
VTR R
R VTR
Figure 1. Logic Diagram
Table 1. TRUTH TABLE
R
H
L
L
*For additional information on our Pb鈭扚ree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
D
x
L
H
CLK
x
Z
Z
Q
L
L
H
Z = LOW to HIGH Transition
x = Don鈥檛 Care
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
漏
Semiconductor Components Industries, LLC, 2007
January, 2007
鈭?/div>
Rev. 2
1
Publication Order Number:
NB4L52/D
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