鈥?/div>
Uses 25 MHz Fundamental Mode Parallel Resonant Crystal
External Loop Filter is Not Required
HCSL Differential Output
Phase Noise:
Offset
Noise Power
100 Hz
-103 dBc/Hz
1 kHz
-1 18 dBc/Hz
10 kHz
-122 dBc/Hz
100 kHz -130 dBc/Hz
1 MHz
-132 dBc/Hz
10 MHz -149 dBc/Hz
Typical Period Jitter RMS of 1.5 ps
Operating Range 3.3 V
鹵10%
Industrial Temperature Range -40擄C to +85擄C
These are Pb-Free Devices
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
VDD
X1/CLK
25 MHz Clock or
Crystal
Clock Buffer
Crystal Oscillator
X2
BN
Phase
Detector
Charge
Pump
VCO
HSCL
Output
HSCL
Output
CLK0
CLK0
CLK1
CLK1
GND
S0
S1
OE
IREF
Figure 1. NB3N5573 Simplified Logic Diagram
漏
Semiconductor Components Industries, LLC, 2007
1
August, 2007 - Rev. 1
Publication Order Number:
NB3N5573/D