鈥?/div>
Input/Output Clock Frequency up to 180 MHz
Low Skew Outputs (50 ps typical)
Output goes to Three鈭扴tate Mode via OE
Operating Range: V
DD
= 3.0 V to 5.5 V
Ideal for Networking Clocks
Packaged in 8鈭抪in SOIC
Industrial Temperature Range
These are Pb鈭扚ree Devices
1
Q1
Q2
CLK
Q3
Q4
DFN8
MN SUFFIX
CASE 506AA
6K
M
G
= Specific Device Code
= Date Code
= Pb鈭扚ree Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
PIN CONNECTIONS
I
CLK
Q1
Q2
Q3
1
2
3
4
OE
Figure 1. Block Diagram
ORDERING INFORMATION
Device
NB3N551DG
NB3N551DR2G
NB3N551MNR4G
Package
SOIC鈭?
(Pb鈭扚ree)
SOIC鈭?
(Pb鈭扚ree)
DFN鈭?
(Pb鈭扚ree)
鈥燜or information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
漏
Semiconductor Components Industries, LLC, 2006
October, 2006
鈭?/div>
Rev. 2
1
Publication Order Number:
NB3N551/D
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