NB2309A
3.3 V Zero Delay
Clock Buffer
The NB2309A is a versatile, 3.3 V zero delay buffer designed to
distribute high鈭抯peed clocks. It accepts one reference input and drives
out nine low鈭抯kew clocks. It is available in a 16 pin package.
The
鈭?H
version of the NB2309A operates at up to 133 MHz, and
has higher drive than the
鈭?
devices. All parts have on鈭抍hip PLL鈥檚 that
lock to an input clock on the REF pin. The PLL feedback is on鈭抍hip
and is obtained from the CLKOUT pad.
The NB2309A has two banks of four outputs each, which can be
controlled by the Select inputs as shown in the Select Input Decoding
Table. If all the output clocks are not required, Bank B can be
three鈭抯tated. The select inputs also allow the input clock to be directly
applied to the outputs for chip and system testing purposes.
Multiple NB2309A devices can accept the same input clock and
distribute it. In this case the skew between the outputs of the two
devices is guaranteed to be less than 700 ps.
All outputs have less than 200 ps of cycle鈭抰o鈭抍ycle jitter. The input
and output propagation delay is guaranteed to be less than 350 ps, and
the output to output skew is guaranteed to be less than 250 ps.
The NB2309A is available in two different configurations, as shown
in the ordering information table. The NB2309A1 is the base part. The
NB2309Ax1H* is the high drive version of the
鈭?
and its rise and fall
times are much faster than
鈭?
part.
Features
http://onsemi.com
MARKING
DIAGRAMS*
16
1
SOIC鈭?6
D SUFFIX
CASE 751B
1
16
16
1
TSSOP鈭?6
DT SUFFIX
CASE 948F
XXXX
A
WL, L
Y
W, WW
G or
G
XXXX
XXXX
ALYWG
G
16
XXXXXXXXG
AWLYWW
1
鈥?/div>
15 MHz to 133 MHz Operating Range, Compatible with CPU and
鈥?/div>
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鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
PCI Bus Frequencies
Zero Input
鈭?/div>
Output Propagation Delay
Multiple Low鈭扴kew Outputs
Output鈭扥utput Skew Less than 250 ps
Device鈭扗evice Skew Less than 700 ps
One Input Drives 9 Outputs, Grouped as 4 + 4 + 1
Less than 200 ps Cycle鈭抰o鈭扖ycle Jitter is Compatible with PentiumR
Based Systems
Test Mode to Bypass PLL
Available in 16 Pin, 150 mil SOIC and 4.4 mm TSSOP
3.3 V Operation, Advanced 0.35
m
CMOS Technology
These are Pb鈭扚ree Devices**
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb鈭扚ree Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
*x = C for Commercial; I for Industrial.
**For additional information on our Pb鈭扚ree strategy and soldering details,
please download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
漏
Semiconductor Components Industries, LLC, 2006
November, 2006
鈭?/div>
Rev. 4
1
Publication Order Number:
NB2309A/D
NB2309AI1HDTG相關(guān)型號PDF文件下載
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英文版
3.3 V Zero Delay Clock Buffer
ONSEMI
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英文版
3.3V Quad Output Zero Delay Buffer
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英文版
3.3 V Zero Delay Clock Buffer
ONSEMI
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英文版
3.3V Five Output Zero Delay Buffer
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英文版
3.3 V Zero Delay Clock Buffer
ONSEMI
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英文版
3.3V Eight Output Zero Delay Buffer
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英文版
3.3 V Zero Delay Clock Buffer
ONSEMI
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英文版
3.3V Nine Output Zero Delay Buffer
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英文版
3.3V Four Output Zero Delay Buffer
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3.3V Five Output Zero Delay Buffer
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英文版
3.3V Nine Output Zero Delay Buffer
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IC BUFFER CLOCK QUAD 3.3V 8-SOIC
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IC BUFFER CLOCK 5OUT 3.3V 8-SOIC
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IC BUFFER CLK 8OUT 3.3V 16-SOIC
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