NB100LVEP91
2.5V / 3.3V Any Level
Positive Input to 鈭?.5V /
鈭?.3V / 鈭?V NECL Output
Translator
The NB100LVEP91 is a triple any level positive input to NECL
output translator. The device accepts LVPECL, LVTTL, LVCMOS,
HSTL, CML or LVDS signals, and translates them to differential
NECL output signals (-2.5 V / -3.3 V / -5 V).
To accomplish the level translation the LVEP91 requires three
power rails. The V
CC
supply should be connected to the positive
supply, and the V
EE
pin should be connected to the negative power
supply. The GND pins are connected to the system ground plane. Both
V
EE
and V
CC
should be bypassed to ground via 0.01
mF
capacitors.
Under open input conditions, the D input will be biased at V
CC
/2
and the D input will be pulled to GND. These conditions will force the
Q outputs to a low, ensuring stability.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01
mF
capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
http://onsemi.com
MARKING
DIAGRAM*
20
1
20
NB100LVEP91
AWLYYWW
SO-20
DW SUFFIX
CASE 751D
1
24
1
24
1
24 PIN QFN
MN SUFFIX
CASE 485L
A
WL, L
YY, Y
WW, W
N100
LP91
ALYW
鈥?/div>
Typical Maximum Frequency > 2.0 GHz
鈥?/div>
430 ps Typical Propagation Delay
鈥?/div>
Operating Range: V
CC
= 2.375 V to 3.8 V;
V
EE
= -2.375 V to -5.5 V; GND = 0 V
鈥?/div>
Q Output will Default LOW with Inputs Open or at GND
= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device
NB100LVEP91DW
NB100LVEP91DWR2
NB100LVEP91MN
NB100LVEP91MNR2
Package
SO-20
SO-20
QFN-24
QFN-24
Shipping
38 Units/Rail
1000/Tape & Reel
93 Units/Rail
3000/Tape & Reel
漏
Semiconductor Components Industries, LLC, 2003
1
January, 2003 - Rev. 2
Publication Order Number:
NB100LVEP91/D
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