NB100LVEP91
2.5 V/3.3 V Any Level
Positive Input to
鈭?.5 V/鈭?.3 V LVNECL
Output Translator
Description
http://onsemi.com
MARKING DIAGRAMS*
20
20
1
The NB100LVEP91 is a triple any level positive input to NECL
output translator. The device accepts LVPECL, LVTTL, LVCMOS,
HSTL, CML or LVDS signals, and translates them to differential
LVNECL output signals (鈭?.5 V /
鈭?.3
V).
To accomplish the level translation the LVEP91 requires three
power rails. The V
CC
pins should be connected to the positive power
supply, and the V
EE
pin should be connected to the negative power
supply. The GND pins are connected to the system ground plane. Both
V
EE
and V
CC
should be bypassed to ground via 0.01
mF
capacitors.
Under open input conditions, the D input will be biased at V
CC
/2
and the D input will be pulled to GND. These conditions will force the
Q outputs to a low state, and Q outputs to a high state, which will
ensure stability.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01
mF
capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
Features
NB100LVEP91
AWLYYWWG
SO鈭?0 WB
DW SUFFIX
CASE 751D
1
24
1
24
1
24 PIN QFN
MN SUFFIX
CASE 485L
A
WL, L
YY, Y
WW, W
G or
G
N100
VP91
ALYWG
G
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Maximum Input Clock Frequency > 2.0 GHz Typical
Maximum Input Data Rate > 2.0 Gb/s Typical
500 ps Typical Propagation Delay
Operating Range: V
CC
= 2.375 V to 3.8 V;
V
EE
=
鈭?.375
V to
鈭?.8
V; GND = 0 V
鈥?/div>
Q Output will Default LOW with Inputs Open or at GND
鈥?/div>
Pb鈭扚ree Packages are Available*
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb鈭扚ree Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
*For additional information on our Pb鈭扚ree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
漏
Semiconductor Components Industries, LLC, 2006
November, 2006
鈭?/div>
Rev. 13
1
Publication Order Number:
NB100LVEP91/D
NB100LVEP91MNG 產(chǎn)品屬性
92
集成電路 (IC)
邏輯 - 變換器
100LVEP
變換器
3
AnyLevel?
LVNECL
2Gbps
3
1
無(wú)/無(wú)
0.675ns
2.375 V ~ 3.8 V
-40°C ~ 85°C
24-VFQFN 裸露焊盤
24-QFN（4x4）
管件
NB100LVEP91MNGOS
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