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NB100LVEP56DTG Datasheet

  • NB100LVEP56DTG

  • 2.5V / 3.3V ECL DUAL Differential 2:1 Multiplexer

  • 10頁

  • ONSEMI

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NB100LVEP56
2.5V / 3.3V ECL DUAL
Differential 2:1 Multiplexer
Description
The NB100LVEP56 is a dual, fully differential 2:1 multiplexer. The
differential data path makes the device ideal for multiplexing low
skew clock or differential data signals. The device features both
individual and common select inputs to address both data path and
random logic applications. Common and individual selects can accept
both LVECL and LVCMOS input voltage levels. Multiple V
BB
pins
are provided.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single鈭抏nded input operation, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01
mF
capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
Features
http://onsemi.com
MARKING
DIAGRAMS*
N100
VP56
ALYWG
G
TSSOP鈭?0
DT SUFFIX
CASE 948E
24
1
24
1
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Maximum Input Clock Frequency > 2.5 GHz Typical
Maximum Input Data Rate > 2.5 Gb/s Typical
525 ps Typical Propagation Delays
Low Profile QFN Package
PECL Mode Operating Range:
V
CC
= 2.375 V to 3.8 V with V
EE
= 0 V
NECL Mode Operating Range:
V
CC
= 0 V with V
EE
=
鈭?.375
V to
鈭?.8
V
Separate, Common Select, and Individual Select
(Compatible with ECL and CMOS Input Voltage Levels)
Q Output Will Default LOW with Inputs Open or at V
EE
Multiple V
BB
Outputs
Pb鈭扚ree Packages are Available
24 PIN QFN
MN SUFFIX
CASE 485L
A
L
Y
W
G
N100
VP56
ALYWG
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb鈭扚ree Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
漏
Semiconductor Components Industries, LLC, 2006
November, 2006
鈭?/div>
Rev. 9
1
Publication Order Number:
NB100LVEP56/D

NB100LVEP56DTG 產(chǎn)品屬性

  • 75

  • 集成電路 (IC)

  • 邏輯 - 信號開關(guān)，多路復(fù)用器，解碼器

  • 100LVEP

  • 差分?jǐn)?shù)字多路復(fù)用器

  • 2 x 2:1

  • 1

  • -

  • 雙電源

  • 2.38 V ~ 3.8 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 20-TSSOP（0.173"，4.40mm 寬）

  • 20-TSSOP

  • 管件

  • NB100LVEP56DTGOS

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